Hi Pali,
On Sat, Sep 24, 2022 at 11:24 AM Pali Rohár <pali@xxxxxxxxxx> wrote:
>
> Simplify pcie-mt7621.c driver code and use new PCI_CONF1_EXT_ADDRESS()
> macro for accessing PCIe config space.
>
> Signed-off-by: Pali Rohár <pali@xxxxxxxxxx>
> ---
> drivers/pci/controller/pcie-mt7621.c | 17 ++++++-----------
> 1 file changed, 6 insertions(+), 11 deletions(-)
I think I have already given my Acked-by and Tested-by for this series
in its RFC version [0]. I don't know if because that was a RFC my tags
are not added to this patch. Anyway:
Acked-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
Thanks,
Sergio Paracuellos
[0]: https://lore.kernel.org/all/CAMhs-H9VHekbXg0avHpYP4=2mHoepnkH8rrshU9ZVnbAB=3h-A@xxxxxxxxxxxxxx/
>
> diff --git a/drivers/pci/controller/pcie-mt7621.c b/drivers/pci/controller/pcie-mt7621.c
> index 33eb37a2225c..4bd1abf26008 100644
> --- a/drivers/pci/controller/pcie-mt7621.c
> +++ b/drivers/pci/controller/pcie-mt7621.c
> @@ -30,6 +30,8 @@
> #include <linux/reset.h>
> #include <linux/sys_soc.h>
>
> +#include "../pci.h"
> +
> /* MediaTek-specific configuration registers */
> #define PCIE_FTS_NUM 0x70c
> #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
> @@ -120,19 +122,12 @@ static inline void pcie_port_write(struct mt7621_pcie_port *port,
> writel_relaxed(val, port->base + reg);
> }
>
> -static inline u32 mt7621_pcie_get_cfgaddr(unsigned int bus, unsigned int slot,
> - unsigned int func, unsigned int where)
> -{
> - return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
> - (func << 8) | (where & 0xfc) | 0x80000000;
> -}
> -
> static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
> unsigned int devfn, int where)
> {
> struct mt7621_pcie *pcie = bus->sysdata;
> - u32 address = mt7621_pcie_get_cfgaddr(bus->number, PCI_SLOT(devfn),
> - PCI_FUNC(devfn), where);
> + u32 address = PCI_CONF1_EXT_ADDRESS(bus->number, PCI_SLOT(devfn),
> + PCI_FUNC(devfn), where);
>
> writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
>
> @@ -147,7 +142,7 @@ static struct pci_ops mt7621_pcie_ops = {
>
> static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
> {
> - u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
> + u32 address = PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg);
>
> pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
> return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
> @@ -156,7 +151,7 @@ static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
> static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
> u32 reg, u32 val)
> {
> - u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
> + u32 address = PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg);
>
> pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
> pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
> --
> 2.20.1
>
