On 9/13/22 02:03, Frank Rowand wrote: > On 9/12/22 01:33, Frank Rowand wrote: >> On 9/2/22 13:54, Rob Herring wrote: >>> On Mon, Aug 29, 2022 at 02:43:37PM -0700, Lizhi Hou wrote: >>>> The PCI endpoint device such as Xilinx Alveo PCI card maps the register >>>> spaces from multiple hardware peripherals to its PCI BAR. Normally, >>>> the PCI core discovers devices and BARs using the PCI enumeration process. >>>> And the process does not provide a way to discover the hardware peripherals >>>> been mapped to PCI BARs. >> >> < snip > >> >>> >>> The above bits aren't really particular to PCI, so they probably >>> belong in the DT core code. Frank will probably have thoughts on what >>> this should look like. >> >> < snip > >> >> I will try to look through this patch series later today (Monday 9/12 >> USA time - I will not be in Dublin for the conferences this week.) >> >> -Frank > > I have collected nearly 500 emails on the history behind this patch and > also another set of patch series that has been trying to achieve some > somewhat similar functionality. Expect me to take a while to wade through > all of this. I'm still working at understanding the full picture of patch 2/2. -Frank > > -Frank
