Like many other ARM PCIe controllers, it uses old PCI Configuration Mechanism #1 from PCI Local Bus for accessing PCI config space. It is not PCIe ECAM in any case. Signed-off-by: Pali Rohár <pali@xxxxxxxxxx> --- drivers/pci/controller/pci-tegra.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 8e323e93be91..5df90d183526 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -395,9 +395,11 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset) } /* - * The configuration space mapping on Tegra is somewhat similar to the ECAM - * defined by PCIe. However it deviates a bit in how the 4 bits for extended - * register accesses are mapped: + * The configuration space mapping on Tegra is somewhat similar to the Intel + * PCI Configuration Mechanism #1 as defined in PCI Local Bus Specification. + * But it is mapped directly into physical address space as opposite of the + * CF8/CFC indirect access, bit 31 (enable) is unset and reserved bits [27:24] + * are used to access extended PCIe config space registers. * * [27:24] extended register number * [23:16] bus number -- 2.20.1
