On Fri, 02 Sep 2022 16:58:00 +0800, Richard Zhu wrote: > Add i.MX8MP PCIe PHY binding. > On iMX8MM, the initialized default value of PERST bit(BIT3) of > SRC_PCIEPHY_RCR is 1b'1. > But i.MX8MP has one inversed default value 1b'0 of PERST bit. > > And the PERST bit should be kept 1b'1 after power and clocks are stable. > So add one more PERST explicitly for i.MX8MP PCIe PHY. > > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx> > Tested-by: Marek Vasut <marex@xxxxxxx> > Tested-by: Richard Leitner <richard.leitner@xxxxxxxxxxx> > Tested-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> > Reviewed-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > --- > .../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
