Add missing aggre0, aggre1 clocks. Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> --- changes since v3: - Changed the order of the clocks added. --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index ad04025..357eae1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2043,7 +2043,9 @@ <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, - <&gcc GCC_DDRSS_PCIE_SF_CLK>; + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; clock-names = "pipe", "pipe_mux", @@ -2055,7 +2057,9 @@ "bus_slave", "slave_q2a", "tbu", - "ddrss_sf_tbu"; + "ddrss_sf_tbu", + "aggre0", + "aggre1"; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; -- 2.7.4
