On 9/7/2022 5:52 PM, Krzysztof Kozlowski wrote:
On 03/09/2022 04:13, Krishna chaitanya chundru wrote:
Add missing aggre0, aggre1 clocks.
Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e66fc67..a5ce095 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2043,6 +2043,8 @@
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_CLK>;
clock-names = "pipe",
@@ -2055,6 +2057,8 @@
"bus_slave",
"slave_q2a",
"tbu",
+ "aggre0",
+ "aggre1",
"ddrss_sf_tbu";
Same as binding - adding entries in the middle causes ABI issues.
Best regards,
Krzysztof
Ok I will change the order as suggested.
