> -----Original Message-----
> From: Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx>
> Sent: 2022年8月31日 18:18
> To: vkoul@xxxxxxxxxx; richard.leitner@xxxxxxxxx;
> alexander.stein@xxxxxxxxxxxxxxx; robh@xxxxxxxxxx; l.stach@xxxxxxxxxxxxxx;
> shawnguo@xxxxxxxxxx; lorenzo.pieralisi@xxxxxxx; p.zabel@xxxxxxxxxxxxxx;
> Hongxing Zhu <hongxing.zhu@xxxxxxx>; bhelgaas@xxxxxxxxxx;
> marex@xxxxxxx
> Cc: linux-phy@xxxxxxxxxxxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx;
> kernel@xxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> linux-kernel@xxxxxxxxxxxxxxx; dl-linux-imx <linux-imx@xxxxxxx>;
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> Subject: Re: [PATCH v5 3/7] arm64: dts: imx8mp-evk: Add PCIe support
>
> On Tue, 2022-08-30 at 15:46 +0800, Richard Zhu wrote:
> > Add PCIe support on i.MX8MP EVK board.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> > Tested-by: Marek Vasut <marex@xxxxxxx>
> > Tested-by: Richard Leitner <richard.leitner@xxxxxxxxxxx>
> > Tested-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 53
> > ++++++++++++++++++++
> > 1 file changed, 53 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > index f6b017ab5f53..defc92a8bb60 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > @@ -5,6 +5,7 @@
> >
> > /dts-v1/;
> >
> > +#include <dt-bindings/phy/phy-imx8-pcie.h>
> > #include "imx8mp.dtsi"
> >
> > / {
> > @@ -33,6 +34,12 @@ memory@40000000 {
> > <0x1 0x00000000 0 0xc0000000>;
> > };
> >
> > + pcie0_refclk: pcie0-refclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > reg_can1_stby: regulator-can1-stby {
> > compatible = "regulator-fixed";
> > regulator-name = "can1-stby"; @@ -55,6 +62,17
> @@
> > reg_can2_stby: regulator-can2-stby {
> > enable-active-high;
> > };
> >
> > + reg_pcie0: regulator-pcie {
> > + compatible = "regulator-fixed";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_pcie0_reg>;
> > + regulator-name = "MPCIE_3V3";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + };
> > +
> > reg_usdhc2_vmmc: regulator-usdhc2 {
> > compatible = "regulator-fixed";
> > pinctrl-names = "default"; @@ -350,6 +368,28 @@
> &i2c5
> > {
> > */
> > };
> >
> > +&pcie_phy {
> > + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> > + clocks = <&pcie0_refclk>;
> > + clock-names = "ref";
> > + status = "okay";
> > +};
> > +
> > +&pcie{
>
> Missing space before that curly brace.
>
Good caught. Would be changed later, thanks.
Best Regards
Richard Zhu
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_pcie0>;
> > + reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
> > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> > + <&clk IMX8MP_CLK_PCIE_ROOT>,
> > + <&clk IMX8MP_CLK_HSIO_AXI>;
> > + clock-names = "pcie", "pcie_aux", "pcie_bus";
> > + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
> > + assigned-clock-rates = <10000000>;
> > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
> > + vpcie-supply = <®_pcie0>;
> > + status = "okay";
> > +};
> > +
> > &snvs_pwrkey {
> > status = "okay";
> > };
> > @@ -502,6 +542,19 @@
> MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL
> > 0x400001c2
> > >;
> > };
> >
> > + pinctrl_pcie0: pcie0grp {
> > + fsl,pins = <
> >
> + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKRE
> Q_B 0x61
> > +/* open drain, pull up */
> >
> + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO
> 07 0x41
> > + >;
> > + };
> > +
> > + pinctrl_pcie0_reg: pcie0reggrp {
> > + fsl,pins = <
> >
> + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO
> 06 0x41
> > + >;
> > + };
> > +
> > pinctrl_pmic: pmicgrp {
> > fsl,pins = <
> > MX8MP_IOMUXC_GPIO1_IO03__GPIO1
> _IO03
> > 0x000001c0
