Instead of implicitly disabling BIT(5) (STRICT_ORDER_ENABLE bit) of the CORE_CTRL2 by writing PCIE_CORE_CTRL2_RESERVED | PCIE_CORE_CTRL2_TD_ENABLE to it, disable it explicitly, with read-modify-write. Signed-off-by: Marek Behún <kabel@xxxxxxxxxx> --- drivers/pci/controller/pci-aardvark.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index e816ab726f66..73a604f70f06 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -600,8 +600,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); /* Program PCIe Control 2 to disable strict ordering */ - reg = PCIE_CORE_CTRL2_RESERVED | - PCIE_CORE_CTRL2_TD_ENABLE; + reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); + reg &= ~PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE; advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); /* Set lane X1 */ -- 2.35.1
