On Fri, Jun 24, 2022 at 05:39:44PM +0300, Serge Semin wrote:
> Depending on the DWC PCIe RC/EP/DM IP-core configuration parameters the
> controllers can be equipped not only with various number of inbound and
> outbound iATU windows, but with varied regions settings like alignment
> (which is also the minimum window size), minimum and maximum sizes. So to
> speak if internal ATU is enabled for the denoted IP-cores then the former
> settings will be defined by the CX_ATU_MIN_REGION_SIZE parameter while the
> later one will be determined by the CX_ATU_MAX_REGION_SIZE configuration
> parameter. Anyway having these parameters used in the driver will help to
> verify whether the requested inbound or outbound memory mappings can be
> fully created. Currently the driver doesn't perform any corresponding
> checking.
>
> Note 1. The extended iATU regions have been supported since DWC PCIe
> v4.60a. There is no need in testing the upper limit register availability
> for the older cores.
>
> Note 2. The regions alignment is determined with using the fls() method
> since the lower four bits of the ATU Limit register can be occupied with
> the Circular Buffer Increment setting, which can be initialized with
> zeros.
>
> The (dma-)ranges verification will be added a bit later in one of the next
> commits.
>
> Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
Thanks,
Mani
> Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 33 +++++++++++++++++---
> drivers/pci/controller/dwc/pcie-designware.h | 2 ++
> 2 files changed, 31 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index f2aa65d02a6c..776752891d11 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -8,9 +8,11 @@
> * Author: Jingoo Han <jg1.han@xxxxxxxxxxx>
> */
>
> +#include <linux/bitops.h>
> #include <linux/delay.h>
> #include <linux/of.h>
> #include <linux/of_platform.h>
> +#include <linux/sizes.h>
> #include <linux/types.h>
>
> #include "../../pci.h"
> @@ -525,7 +527,8 @@ static bool dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
> static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci)
> {
> int max_region, ob, ib;
> - u32 val;
> + u32 val, min, dir;
> + u64 max;
>
> if (pci->iatu_unroll_enabled) {
> max_region = min((int)pci->atu_size / 512, 256);
> @@ -548,8 +551,29 @@ static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci)
> break;
> }
>
> - pci->num_ib_windows = ib;
> + if (ob) {
> + dir = PCIE_ATU_REGION_DIR_OB;
> + } else if (ib) {
> + dir = PCIE_ATU_REGION_DIR_IB;
> + } else {
> + dev_err(pci->dev, "No iATU regions found\n");
> + return;
> + }
> +
> + dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_LIMIT, 0x0);
> + min = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_LIMIT);
> +
> + if (dw_pcie_ver_is_ge(pci, 460A)) {
> + dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF);
> + max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT);
> + } else {
> + max = 0;
> + }
> +
> pci->num_ob_windows = ob;
> + pci->num_ib_windows = ib;
> + pci->region_align = 1 << fls(min);
> + pci->region_limit = (max << 32) | (SZ_4G - 1);
> }
>
> void dw_pcie_iatu_detect(struct dw_pcie *pci)
> @@ -582,8 +606,9 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
> dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
> "enabled" : "disabled");
>
> - dev_info(pci->dev, "Detected iATU regions: %u outbound, %u inbound\n",
> - pci->num_ob_windows, pci->num_ib_windows);
> + dev_info(pci->dev, "iATU regions: %u ob, %u ib, align %uK, limit %lluG\n",
> + pci->num_ob_windows, pci->num_ib_windows,
> + pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G);
> }
>
> void dw_pcie_setup(struct dw_pcie *pci)
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index c18f0db09b31..25c86771c810 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -272,6 +272,8 @@ struct dw_pcie {
> size_t atu_size;
> u32 num_ib_windows;
> u32 num_ob_windows;
> + u32 region_align;
> + u64 region_limit;
> struct dw_pcie_rp pp;
> struct dw_pcie_ep ep;
> const struct dw_pcie_ops *ops;
> --
> 2.35.1
>
--
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