The PCIe QMP PHY requires different programming sequences when being
used for the RC (Root Complex) or for the EP (End Point) modes. Allow
selecting the submode and thus selecting a set of PHY programming
tables.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 41 ++++++++++++++++--------
1 file changed, 28 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index e6272bd3d735..af3577a5d7e4 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1369,10 +1369,14 @@ struct qmp_phy_cfg {
/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
struct qmp_phy_cfg_tables primary;
/*
- * Init sequence for PHY blocks, providing additional register
- * programming. Unless required it can be left omitted.
+ * Init sequences for PHY blocks, providing additional register
+ * programming. They are used for providing separate sequences for the
+ * Root Complex and for the End Point usecases.
+ *
+ * If EP mode is not supported, both tables can be left empty.
*/
- struct qmp_phy_cfg_tables secondary;
+ struct qmp_phy_cfg_tables secondary_rc; /* for the RC only */
+ struct qmp_phy_cfg_tables secondary_ep; /* for the EP only */
/* clock ids to be requested */
const char * const *clk_list;
@@ -1422,6 +1426,7 @@ struct qmp_phy_cfg {
* @index: lane index
* @qmp: QMP phy to which this lane belongs
* @mode: current PHY mode
+ * @secondary: currently selected PHY secondary init table set
*/
struct qmp_phy {
struct phy *phy;
@@ -1434,6 +1439,7 @@ struct qmp_phy {
void __iomem *rx2;
void __iomem *pcs_misc;
struct clk *pipe_clk;
+ const struct qmp_phy_cfg_tables *secondary;
unsigned int index;
struct qcom_qmp *qmp;
enum phy_mode mode;
@@ -1687,7 +1693,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
.pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
.pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
},
- .secondary = {
+ .secondary_rc = {
.serdes_tbl = sm8250_qmp_gen3x1_pcie_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
.rx_tbl = sm8250_qmp_gen3x1_pcie_rx_tbl,
@@ -1730,7 +1736,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
.pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
.pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
},
- .secondary = {
+ .secondary_rc = {
.tx_tbl = sm8250_qmp_gen3x2_pcie_tx_tbl,
.tx_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
.rx_tbl = sm8250_qmp_gen3x2_pcie_rx_tbl,
@@ -1955,7 +1961,7 @@ static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy)
void __iomem *serdes = qphy->serdes;
qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->primary.serdes_tbl, cfg->primary.serdes_tbl_num);
- qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->secondary.serdes_tbl, cfg->secondary.serdes_tbl_num);
+ qcom_qmp_phy_pcie_configure(serdes, cfg->regs, qphy->secondary->serdes_tbl, qphy->secondary->serdes_tbl_num);
return 0;
}
@@ -2049,6 +2055,10 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
unsigned int mask, val, ready;
int ret;
+ /* Default to RC mode if no mode was selected */
+ if (!qphy->secondary)
+ qphy->secondary = &cfg->secondary_rc;
+
qcom_qmp_phy_pcie_serdes_init(qphy);
ret = clk_prepare_enable(qphy->pipe_clk);
@@ -2061,39 +2071,39 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs,
cfg->primary.tx_tbl, cfg->primary.tx_tbl_num, 1);
qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs,
- cfg->secondary.tx_tbl, cfg->secondary.tx_tbl_num, 1);
+ qphy->secondary->tx_tbl, qphy->secondary->tx_tbl_num, 1);
/* Configuration for other LANE for USB-DP combo PHY */
if (cfg->is_dual_lane_phy) {
qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs,
cfg->primary.tx_tbl, cfg->primary.tx_tbl_num, 2);
qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs,
- cfg->secondary.tx_tbl, cfg->secondary.tx_tbl_num, 2);
+ qphy->secondary->tx_tbl, qphy->secondary->tx_tbl_num, 2);
}
qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs,
cfg->primary.rx_tbl, cfg->primary.rx_tbl_num, 1);
qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs,
- cfg->secondary.rx_tbl, cfg->secondary.rx_tbl_num, 1);
+ qphy->secondary->rx_tbl, qphy->secondary->rx_tbl_num, 1);
if (cfg->is_dual_lane_phy) {
qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs,
cfg->primary.rx_tbl, cfg->primary.rx_tbl_num, 2);
qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs,
- cfg->secondary.rx_tbl, cfg->secondary.rx_tbl_num, 2);
+ qphy->secondary->rx_tbl, qphy->secondary->rx_tbl_num, 2);
}
qcom_qmp_phy_pcie_configure(pcs, cfg->regs,
cfg->primary.pcs_tbl, cfg->primary.pcs_tbl_num);
qcom_qmp_phy_pcie_configure(pcs, cfg->regs,
- cfg->secondary.pcs_tbl, cfg->secondary.pcs_tbl_num);
+ qphy->secondary->pcs_tbl, qphy->secondary->pcs_tbl_num);
qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs,
cfg->primary.pcs_misc_tbl,
cfg->primary.pcs_misc_tbl_num);
qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs,
- cfg->secondary.pcs_misc_tbl,
- cfg->secondary.pcs_misc_tbl_num);
+ qphy->secondary->pcs_misc_tbl,
+ qphy->secondary->pcs_misc_tbl_num);
/*
* Pull out PHY from POWER DOWN state.
@@ -2195,6 +2205,11 @@ static int qcom_qmp_phy_pcie_set_mode(struct phy *phy,
qphy->mode = mode;
+ if (submode)
+ qphy->secondary = &qphy->cfg->secondary_ep;
+ else
+ qphy->secondary = &qphy->cfg->secondary_rc;
+
return 0;
}
--
2.35.1
