On Fri, Jul 15, 2022 at 6:38 PM Ben Chuang <benchuanggli@xxxxxxxxx> wrote:
>
> On Tue, Jul 5, 2022 at 2:00 PM Vidya Sagar <vidyas@xxxxxxxxxx> wrote:
> >
> > Previously ASPM L1 Substates control registers (CTL1 and CTL2) weren't
> > saved and restored during suspend/resume leading to L1 Substates
> > configuration being lost post-resume.
> >
> > Save the L1 Substates control registers so that the configuration is
> > retained post-resume.
> >
> > Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
> > Tested-by: Abhishek Sahu <abhsahu@xxxxxxxxxx>
>
> Hi Vidya,
>
> I tested this patch on kernel v5.19-rc6.
> The test device is GL9755 card reader controller on Intel i5-10210U RVP.
> This patch can restore L1SS after suspend/resume.
>
> The test results are as follows:
>
> After Boot:
> #lspci -d 17a0:9755 -vvv | grep -A5 "L1 PM Substates"
> Capabilities: [110 v1] L1 PM Substates
> L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+
> ASPM_L1.1+ L1_PM_Substates+
> PortCommonModeRestoreTime=255us
> PortTPowerOnTime=3100us
> L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
> T_CommonMode=0us LTR1.2_Threshold=3145728ns
> L1SubCtl2: T_PwrOn=3100us
>
>
> After suspend/resume without this patch.
> #lspci -d 17a0:9755 -vvv | grep -A5 "L1 PM Substates"
> Capabilities: [110 v1] L1 PM Substates
> L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+
> ASPM_L1.1+ L1_PM_Substates+
> PortCommonModeRestoreTime=255us
> PortTPowerOnTime=3100us
> L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
> T_CommonMode=0us LTR1.2_Threshold=0ns
> L1SubCtl2: T_PwrOn=10us
>
>
> After suspend/resume with this patch.
> #lspci -d 17a0:9755 -vvv | grep -A5 "L1 PM Substates"
> Capabilities: [110 v1] L1 PM Substates
> L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+
> ASPM_L1.1+ L1_PM_Substates+
> PortCommonModeRestoreTime=255us
> PortTPowerOnTime=3100us
> L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
> T_CommonMode=0us LTR1.2_Threshold=3145728ns
> L1SubCtl2: T_PwrOn=3100us
>
>
> Tested-by: Ben Chuang <benchuanggli@xxxxxxxxx>
Forgot to add mine:
Tested-by: Kai-Heng Feng <kai.heng.feng@xxxxxxxxxxxxx>
>
> Best regards,
> Ben Chuang
>
>
> > ---
> > Hi,
> > Kenneth R. Crudup <kenny@xxxxxxxxx>, Could you please verify this patch
> > on your laptop (Dell XPS 13) one last time?
> > IMHO, the regression observed on your laptop with an old version of the patch
> > could be due to a buggy old version BIOS in the laptop.
> >
> > Thanks,
> > Vidya Sagar
> >
> > drivers/pci/pci.c | 7 +++++++
> > drivers/pci/pci.h | 4 ++++
> > drivers/pci/pcie/aspm.c | 44 +++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 55 insertions(+)
> >
> > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> > index cfaf40a540a8..aca05880aaa3 100644
> > --- a/drivers/pci/pci.c
> > +++ b/drivers/pci/pci.c
> > @@ -1667,6 +1667,7 @@ int pci_save_state(struct pci_dev *dev)
> > return i;
> >
> > pci_save_ltr_state(dev);
> > + pci_save_aspm_l1ss_state(dev);
> > pci_save_dpc_state(dev);
> > pci_save_aer_state(dev);
> > pci_save_ptm_state(dev);
> > @@ -1773,6 +1774,7 @@ void pci_restore_state(struct pci_dev *dev)
> > * LTR itself (in the PCIe capability).
> > */
> > pci_restore_ltr_state(dev);
> > + pci_restore_aspm_l1ss_state(dev);
> >
> > pci_restore_pcie_state(dev);
> > pci_restore_pasid_state(dev);
> > @@ -3489,6 +3491,11 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev)
> > if (error)
> > pci_err(dev, "unable to allocate suspend buffer for LTR\n");
> >
> > + error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_L1SS,
> > + 2 * sizeof(u32));
> > + if (error)
> > + pci_err(dev, "unable to allocate suspend buffer for ASPM-L1SS\n");
> > +
> > pci_allocate_vc_save_buffers(dev);
> > }
> >
> > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> > index e10cdec6c56e..92d8c92662a4 100644
> > --- a/drivers/pci/pci.h
> > +++ b/drivers/pci/pci.h
> > @@ -562,11 +562,15 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev);
> > void pcie_aspm_exit_link_state(struct pci_dev *pdev);
> > void pcie_aspm_pm_state_change(struct pci_dev *pdev);
> > void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
> > +void pci_save_aspm_l1ss_state(struct pci_dev *dev);
> > +void pci_restore_aspm_l1ss_state(struct pci_dev *dev);
> > #else
> > static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
> > static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
> > static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
> > static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
> > +static inline void pci_save_aspm_l1ss_state(struct pci_dev *dev) { }
> > +static inline void pci_restore_aspm_l1ss_state(struct pci_dev *dev) { }
> > #endif
> >
> > #ifdef CONFIG_PCIE_ECRC
> > diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> > index a96b7424c9bc..2c29fdd20059 100644
> > --- a/drivers/pci/pcie/aspm.c
> > +++ b/drivers/pci/pcie/aspm.c
> > @@ -726,6 +726,50 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
> > PCI_L1SS_CTL1_L1SS_MASK, val);
> > }
> >
> > +void pci_save_aspm_l1ss_state(struct pci_dev *dev)
> > +{
> > + int aspm_l1ss;
> > + struct pci_cap_saved_state *save_state;
> > + u32 *cap;
> > +
> > + if (!pci_is_pcie(dev))
> > + return;
> > +
> > + aspm_l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
> > + if (!aspm_l1ss)
> > + return;
> > +
> > + save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_L1SS);
> > + if (!save_state)
> > + return;
> > +
> > + cap = (u32 *)&save_state->cap.data[0];
> > + pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL2, cap++);
> > + pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, cap++);
> > +}
> > +
> > +void pci_restore_aspm_l1ss_state(struct pci_dev *dev)
> > +{
> > + int aspm_l1ss;
> > + struct pci_cap_saved_state *save_state;
> > + u32 *cap;
> > +
> > + if (!pci_is_pcie(dev))
> > + return;
> > +
> > + aspm_l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
> > + if (!aspm_l1ss)
> > + return;
> > +
> > + save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_L1SS);
> > + if (!save_state)
> > + return;
> > +
> > + cap = (u32 *)&save_state->cap.data[0];
> > + pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL2, *cap++);
> > + pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, *cap++);
> > +}
> > +
> > static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
> > {
> > pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
> > --
> > 2.17.1
> >
