On Thu, 14 Jul 2022 17:02:52 -0700 Dan Williams <dan.j.williams@xxxxxxxxx> wrote: > CXL regions (interleave sets) are made up of a set of memory devices > where each device maps a portion of the interleave with one of its > decoders (see CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure). > As endpoint decoders are identified by a provisioning tool they can be > added to a region provided the region interleave properties are set > (way, granularity, HPA) and DPA has been assigned to the decoder. > > The attach event triggers several validation checks, for example: > - is the DPA sized appropriately for the region > - is the decoder reachable via the host-bridges identified by the > region's root decoder > - is the device already active in a different region position slot > - are there already regions with a higher HPA active on a given port > (per CXL 2.0 8.2.5.12.20 Committing Decoder Programming) > > ...and the attach event affords an opportunity to collect data and > resources relevant to later programming the target lists in switch > decoders, for example: > - allocate a decoder at each cxl_port in the decode chain > - for a given switch port, how many the region's endpoints are hosted > through the port > - how many unique targets (next hops) does a port need to map to reach > those endpoints > > The act of reconciling this information and deploying it to the decoder > configuration is saved for a follow-on patch. > > Co-developed-by: Ben Widawsky <bwidawsk@xxxxxxxxxx> > Signed-off-by: Ben Widawsky <bwidawsk@xxxxxxxxxx> > Signed-off-by: Dan Williams <dan.j.williams@xxxxxxxxx> All the review comment resolutions from v1 look good to me. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx> Thanks, Jonathan
