[+cc Kai-Heng] On Wed, Jul 13, 2022 at 11:29:42PM +0530, Vidya Sagar wrote: > Hi, > @Kenneth, Could you please verify it on your laptop one last time? > > @Bjorn, Could you please review this change in the meanwhile? Seems like this may be related to Kai-Heng's patch: https://lore.kernel.org/r/20220509073639.2048236-1-kai.heng.feng@xxxxxxxxxxxxx since he specifically mentioned L1SS. I applied Kai-Heng's patch for v5.20 yesterday, but I haven't worked out the connection to this patch. But if you want Kenneth to test this, it should probably be on top of Kai-Heng's patch so we're testing something close to the eventual result. > On 7/5/2022 11:30 AM, Vidya Sagar wrote: > > External email: Use caution opening links or attachments > > > > > > Previously ASPM L1 Substates control registers (CTL1 and CTL2) weren't > > saved and restored during suspend/resume leading to L1 Substates > > configuration being lost post-resume. > > > > Save the L1 Substates control registers so that the configuration is > > retained post-resume. > > > > Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx> > > Tested-by: Abhishek Sahu <abhsahu@xxxxxxxxxx> > > --- > > Hi, > > Kenneth R. Crudup <kenny@xxxxxxxxx>, Could you please verify this patch > > on your laptop (Dell XPS 13) one last time? > > IMHO, the regression observed on your laptop with an old version of the patch > > could be due to a buggy old version BIOS in the laptop. > > > > Thanks, > > Vidya Sagar > > > > drivers/pci/pci.c | 7 +++++++ > > drivers/pci/pci.h | 4 ++++ > > drivers/pci/pcie/aspm.c | 44 +++++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 55 insertions(+) > > > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > > index cfaf40a540a8..aca05880aaa3 100644 > > --- a/drivers/pci/pci.c > > +++ b/drivers/pci/pci.c > > @@ -1667,6 +1667,7 @@ int pci_save_state(struct pci_dev *dev) > > return i; > > > > pci_save_ltr_state(dev); > > + pci_save_aspm_l1ss_state(dev); > > pci_save_dpc_state(dev); > > pci_save_aer_state(dev); > > pci_save_ptm_state(dev); > > @@ -1773,6 +1774,7 @@ void pci_restore_state(struct pci_dev *dev) > > * LTR itself (in the PCIe capability). > > */ > > pci_restore_ltr_state(dev); > > + pci_restore_aspm_l1ss_state(dev); > > > > pci_restore_pcie_state(dev); > > pci_restore_pasid_state(dev); > > @@ -3489,6 +3491,11 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev) > > if (error) > > pci_err(dev, "unable to allocate suspend buffer for LTR\n"); > > > > + error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_L1SS, > > + 2 * sizeof(u32)); > > + if (error) > > + pci_err(dev, "unable to allocate suspend buffer for ASPM-L1SS\n"); > > + > > pci_allocate_vc_save_buffers(dev); > > } > > > > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > > index e10cdec6c56e..92d8c92662a4 100644 > > --- a/drivers/pci/pci.h > > +++ b/drivers/pci/pci.h > > @@ -562,11 +562,15 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev); > > void pcie_aspm_exit_link_state(struct pci_dev *pdev); > > void pcie_aspm_pm_state_change(struct pci_dev *pdev); > > void pcie_aspm_powersave_config_link(struct pci_dev *pdev); > > +void pci_save_aspm_l1ss_state(struct pci_dev *dev); > > +void pci_restore_aspm_l1ss_state(struct pci_dev *dev); > > #else > > static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } > > static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } > > static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } > > static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } > > +static inline void pci_save_aspm_l1ss_state(struct pci_dev *dev) { } > > +static inline void pci_restore_aspm_l1ss_state(struct pci_dev *dev) { } > > #endif > > > > #ifdef CONFIG_PCIE_ECRC > > diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c > > index a96b7424c9bc..2c29fdd20059 100644 > > --- a/drivers/pci/pcie/aspm.c > > +++ b/drivers/pci/pcie/aspm.c > > @@ -726,6 +726,50 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) > > PCI_L1SS_CTL1_L1SS_MASK, val); > > } > > > > +void pci_save_aspm_l1ss_state(struct pci_dev *dev) > > +{ > > + int aspm_l1ss; > > + struct pci_cap_saved_state *save_state; > > + u32 *cap; > > + > > + if (!pci_is_pcie(dev)) > > + return; > > + > > + aspm_l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); > > + if (!aspm_l1ss) > > + return; > > + > > + save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_L1SS); > > + if (!save_state) > > + return; > > + > > + cap = (u32 *)&save_state->cap.data[0]; > > + pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL2, cap++); > > + pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, cap++); > > +} > > + > > +void pci_restore_aspm_l1ss_state(struct pci_dev *dev) > > +{ > > + int aspm_l1ss; > > + struct pci_cap_saved_state *save_state; > > + u32 *cap; > > + > > + if (!pci_is_pcie(dev)) > > + return; > > + > > + aspm_l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); > > + if (!aspm_l1ss) > > + return; > > + > > + save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_L1SS); > > + if (!save_state) > > + return; > > + > > + cap = (u32 *)&save_state->cap.data[0]; > > + pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL2, *cap++); > > + pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, *cap++); > > +} > > + > > static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) > > { > > pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, > > -- > > 2.17.1 > >
