[+cc Robert since I resolved a conflict in his patch, -cc stable]
On Sat, Jul 09, 2022 at 03:03:34AM +0200, Christian Marangi wrote:
> On Fri, Jul 08, 2022 at 06:01:55PM -0500, Bjorn Helgaas wrote:
> > On Sat, Jul 09, 2022 at 12:27:43AM +0200, Christian Marangi wrote:
> > > We currently enable clocks BEFORE we write to PARF_PHY_CTRL reg to
> > > enable clocks and resets. This case the driver to never set to a ready
> > > state with the error 'Phy link never came up'.
> > >
> > > This in fact is caused by the phy clock getting enabled before setting
> > > the required bits in the PARF regs.
> > >
> > > A workaround for this was set but with this new discovery we can drop
> > > the workaround and use a proper solution to the problem by just enabling
> > > the clock only AFTER the PARF_PHY_CTRL bit is set.
> > >
> > > This correctly setup the pcie line and makes it usable even when a
> > > bootloader leave the pcie line to a underfined state.
> >
> > Is "pcie" here a signal name? Maybe this refers to the "PCIe link"?
>
> no i was referring to PCIe link. Fell free to fix it if it's not a
> problem (or if you want i can just resend)
I fixed it.
> Think something went wrong in the rebase as the patch fixup is reverted.
>
> 11946f8b6e77a6794c111aafef7772e9967d9a54 is still wrong.
>
> clk_bulk_prepare_enable must be after
> writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
> so in the post init.
My error, sorry. I updated it, current head:
1a88605a3efd ("dt-bindings: PCI: qcom: Fix description typo")
Robert, your patch that I updated is:
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git/commit/?h=pci/ctrl/qcom-pending&id=cdb32283bcf202d0db512abb80794056d44e7e9f
It would still be nice to get an ack from one of the maintainers for
this.
Bjorn
