On Mon, Jul 04, 2022 at 06:27:43PM +0300, Dmitry Baryshkov wrote: > Split handling of MSI host IRQs to a separate dw_pcie_msi_host_init() > function. The code is complex enough to warrant a separate function. > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > Reviewed-by: Johan Hovold <johan+linaro@xxxxxxxxxx> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> Thanks, Mani > --- > .../pci/controller/dwc/pcie-designware-host.c | 101 ++++++++++-------- > 1 file changed, 57 insertions(+), 44 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 4c5b3f70ab17..3ba531da99d4 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -290,6 +290,61 @@ static void dw_pcie_msi_init(struct pcie_port *pp) > dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); > } > > +static int dw_pcie_msi_host_init(struct pcie_port *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct device *dev = pci->dev; > + struct platform_device *pdev = to_platform_device(dev); > + int ret; > + u32 ctrl, num_ctrls; > + > + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; > + for (ctrl = 0; ctrl < num_ctrls; ctrl++) > + pp->irq_mask[ctrl] = ~0; > + > + if (!pp->msi_irq[0]) { > + int irq = platform_get_irq_byname_optional(pdev, "msi"); > + > + if (irq < 0) { > + irq = platform_get_irq(pdev, 0); > + if (irq < 0) > + return irq; > + } > + pp->msi_irq[0] = irq; > + } > + > + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; > + > + ret = dw_pcie_allocate_domains(pp); > + if (ret) > + return ret; > + > + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { > + if (pp->msi_irq[ctrl] > 0) > + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], > + dw_chained_msi_isr, > + pp); > + } > + > + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); > + if (ret) > + dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); > + > + pp->msi_page = alloc_page(GFP_DMA32); > + pp->msi_data = dma_map_page(pci->dev, pp->msi_page, 0, > + PAGE_SIZE, DMA_FROM_DEVICE); > + ret = dma_mapping_error(pci->dev, pp->msi_data); > + if (ret) { > + dev_err(pci->dev, "Failed to map MSI data\n"); > + pp->msi_page = NULL; > + pp->msi_data = 0; > + dw_pcie_free_msi(pp); > + return ret; > + } > + > + return 0; > +} > + > int dw_pcie_host_init(struct pcie_port *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > @@ -367,51 +422,9 @@ int dw_pcie_host_init(struct pcie_port *pp) > if (ret < 0) > return ret; > } else if (pp->has_msi_ctrl) { > - u32 ctrl, num_ctrls; > - > - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; > - for (ctrl = 0; ctrl < num_ctrls; ctrl++) > - pp->irq_mask[ctrl] = ~0; > - > - if (!pp->msi_irq[0]) { > - int irq = platform_get_irq_byname_optional(pdev, "msi"); > - > - if (irq < 0) { > - irq = platform_get_irq(pdev, 0); > - if (irq < 0) > - return irq; > - } > - pp->msi_irq[0] = irq; > - } > - > - pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; > - > - ret = dw_pcie_allocate_domains(pp); > - if (ret) > + ret = dw_pcie_msi_host_init(pp); > + if (ret < 0) > return ret; > - > - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { > - if (pp->msi_irq[ctrl] > 0) > - irq_set_chained_handler_and_data(pp->msi_irq[ctrl], > - dw_chained_msi_isr, > - pp); > - } > - > - ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); > - if (ret) > - dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); > - > - pp->msi_page = alloc_page(GFP_DMA32); > - pp->msi_data = dma_map_page(pci->dev, pp->msi_page, 0, > - PAGE_SIZE, DMA_FROM_DEVICE); > - ret = dma_mapping_error(pci->dev, pp->msi_data); > - if (ret) { > - dev_err(pci->dev, "Failed to map MSI data\n"); > - __free_page(pp->msi_page); > - pp->msi_page = NULL; > - pp->msi_data = 0; > - goto err_free_msi; > - } > } > } > > -- > 2.35.1 > -- மணிவண்ணன் சதாசிவம்