On Mon, 27 Jun 2022 21:15:21 -0700
ira.weiny@xxxxxxxxx wrote:
> From: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
>
> Introduced in a PCIe r6.0, sec 6.30, DOE provides a config space based
> mailbox with standard protocol discovery. Each mailbox is accessed
> through a DOE Extended Capability.
>
> Each DOE mailbox must support the DOE discovery protocol in addition to
> any number of additional protocols.
>
> Define core PCIe functionality to manage a single PCIe DOE mailbox at a
> defined config space offset. Functionality includes iterating,
> creating, query of supported protocol, and task submission. Destruction
> of the mailboxes is device managed.
>
> If interrupts are desired, the interrupt number can be queried and
> passed to the create function. Passing a negative value disables
> interrupts for that mailbox. It is the caller's responsibility to ensure
> enough interrupt vectors are allocated.
>
> Cc: "Li, Ming" <ming4.li@xxxxxxxxx>
> Cc: Bjorn Helgaas <helgaas@xxxxxxxxxx>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
> Co-developed-by: Ira Weiny <ira.weiny@xxxxxxxxx>
> Signed-off-by: Ira Weiny <ira.weiny@xxxxxxxxx>
+static void *pci_doe_xa_entry(u16 vid, u8 prot)
+{
+ return (void *)(((unsigned long)vid << 16) | prot);
+}
...
> +static int pci_doe_cache_protocols(struct pci_doe_mb *doe_mb)
> +{
> + u8 index = 0;
> + u8 xa_idx = 0;
> +
> + do {
> + int rc;
> + u16 vid;
> + u8 prot;
> +
> + rc = pci_doe_discovery(doe_mb, &index, &vid, &prot);
> + if (rc)
> + return rc;
> +
> + pci_dbg(doe_mb->pdev,
> + "[%x] Found protocol %d vid: %x prot: %x\n",
> + doe_mb->cap_offset, xa_idx, vid, prot);
> +
> + rc = xa_insert(&doe_mb->prots, xa_idx++,
> + pci_doe_xa_entry(vid, prot), GFP_KERNEL);
I'm not that familiar with xarray, but the docs suggest that you have
to use xa_mk_value() to store an integer directly into it.
> + if (rc)
> + return -ENOMEM;
> + } while (index);
> +
> + return 0;
> +}
> +
