[+cc Marc, IRQ affinity vs chained IRQ handlers]
On Thu, Jun 23, 2022 at 06:32:40PM +0200, Pali Rohár wrote:
> On Thursday 23 June 2022 11:27:47 Bjorn Helgaas wrote:
> > On Tue, May 24, 2022 at 02:28:17PM +0200, Pali Rohár wrote:
> > > Same as in commit a3b69dd0ad62 ("Revert "PCI: aardvark: Rewrite
> > > IRQ code to chained IRQ handler"") for pci-aardvark driver, use
> > > devm_request_irq() instead of chained IRQ handler in pci-mvebu.c
> > > driver.
> > >
> > > This change fixes affinity support and allows to pin interrupts
> > > from different PCIe controllers to different CPU cores.
> >
> > Several other drivers use irq_set_chained_handler_and_data(). Do
> > any of them need similar changes?
>
> I do not know. This needs testing on HW which use those other
> drivers.
>
> > The commit log suggests that using chained IRQ handlers breaks
> > affinity support. But perhaps that's not the case and the real
> > culprit is some other difference between mvebu and the other
> > drivers.
>
> It is possible. But similar patch (revert; linked below) was
> required for aardvark. I tested same approach on mvebu and it fixed
> affinity support.
This feels like something we should understand better. If
irq_set_chained_handler_and_data() is a problem for affinity, we
should fix it across the board in all the drivers at once.
If the real problem is something different, we should figure that out
and document it in the commit log.
I cc'd Marc in case he has time to educate us.
> > > Fixes: ec075262648f ("PCI: mvebu: Implement support for legacy INTx interrupts")
> > > Signed-off-by: Pali Rohár <pali@xxxxxxxxxx>
> > > ---
> > > Hello Bjorn! This is basically same issue as for pci-aardvark.c:
> > > https://lore.kernel.org/linux-pci/20220515125815.30157-1-pali@xxxxxxxxxx/#t
> > >
> > > I tested this patch with pci=nomsi in cmdline (to force kernel to use
> > > legacy intx instead of MSI) on A385 and checked that I can set affinity
> > > via /proc/irq/XX/smp_affinity file for every mvebu pcie controller to
> > > different CPU and legacy interrupts from different cards/controllers
> > > were handled by different CPUs.
> > >
> > > I think that this is important on Armada XP platforms which have many
> > > independent PCIe controllers (IIRC up to 10) and many cores (up to 4).
> > > ---
> > > drivers/pci/controller/pci-mvebu.c | 30 +++++++++++++++++-------------
> > > 1 file changed, 17 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
> > > index 8f76d4bda356..de67ea39fea5 100644
> > > --- a/drivers/pci/controller/pci-mvebu.c
> > > +++ b/drivers/pci/controller/pci-mvebu.c
> > > @@ -1017,16 +1017,13 @@ static int mvebu_pcie_init_irq_domain(struct mvebu_pcie_port *port)
> > > return 0;
> > > }
> > >
> > > -static void mvebu_pcie_irq_handler(struct irq_desc *desc)
> > > +static irqreturn_t mvebu_pcie_irq_handler(int irq, void *arg)
> > > {
> > > - struct mvebu_pcie_port *port = irq_desc_get_handler_data(desc);
> > > - struct irq_chip *chip = irq_desc_get_chip(desc);
> > > + struct mvebu_pcie_port *port = arg;
> > > struct device *dev = &port->pcie->pdev->dev;
> > > u32 cause, unmask, status;
> > > int i;
> > >
> > > - chained_irq_enter(chip, desc);
> > > -
> > > cause = mvebu_readl(port, PCIE_INT_CAUSE_OFF);
> > > unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
> > > status = cause & unmask;
> > > @@ -1040,7 +1037,7 @@ static void mvebu_pcie_irq_handler(struct irq_desc *desc)
> > > dev_err_ratelimited(dev, "unexpected INT%c IRQ\n", (char)i+'A');
> > > }
> > >
> > > - chained_irq_exit(chip, desc);
> > > + return status ? IRQ_HANDLED : IRQ_NONE;
> > > }
> > >
> > > static int mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
> > > @@ -1490,9 +1487,20 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
> > > mvebu_pcie_powerdown(port);
> > > continue;
> > > }
> > > - irq_set_chained_handler_and_data(irq,
> > > - mvebu_pcie_irq_handler,
> > > - port);
> > > +
> > > + ret = devm_request_irq(dev, irq, mvebu_pcie_irq_handler,
> > > + IRQF_SHARED | IRQF_NO_THREAD,
> > > + port->name, port);
> > > + if (ret) {
> > > + dev_err(dev, "%s: cannot register interrupt handler: %d\n",
> > > + port->name, ret);
> > > + irq_domain_remove(port->intx_irq_domain);
> > > + pci_bridge_emul_cleanup(&port->bridge);
> > > + devm_iounmap(dev, port->base);
> > > + port->base = NULL;
> > > + mvebu_pcie_powerdown(port);
> > > + continue;
> > > + }
> > > }
> > >
> > > /*
> > > @@ -1599,7 +1607,6 @@ static int mvebu_pcie_remove(struct platform_device *pdev)
> > >
> > > for (i = 0; i < pcie->nports; i++) {
> > > struct mvebu_pcie_port *port = &pcie->ports[i];
> > > - int irq = port->intx_irq;
> > >
> > > if (!port->base)
> > > continue;
> > > @@ -1615,9 +1622,6 @@ static int mvebu_pcie_remove(struct platform_device *pdev)
> > > /* Clear all interrupt causes. */
> > > mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF);
> > >
> > > - if (irq > 0)
> > > - irq_set_chained_handler_and_data(irq, NULL, NULL);
> > > -
> > > /* Remove IRQ domains. */
> > > if (port->intx_irq_domain)
> > > irq_domain_remove(port->intx_irq_domain);
> > > --
> > > 2.20.1
> > >
