> On Sat, 18 Jun 2022 08:14:58 +0530, Bharat Kumar Gogada wrote: > > Xilinx Versal Premium series has CPM5 block which supports Root Port > > functionality at Gen5 speed. > > > > Add support for YAML schemas documentation for Versal CPM5 Root Port > driver. > > > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xxxxxxxxxx> > > --- > > .../bindings/pci/xilinx-versal-cpm.yaml | 38 ++++++++++++++++++- > > 1 file changed, 37 insertions(+), 1 deletion(-) > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m > dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > ./Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml:17:7: > [warning] wrong indentation: expected 4 but found 6 (indentation) > > dtschema/dtc warnings/errors: > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/patch/ > > This check can fail if there are any dependencies. The base for a patch series > is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above error(s), > then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit. Hi Rob, will check and re submit. Regards, Bharat
