> -----Original Message-----
> From: Bjorn Helgaas <helgaas@xxxxxxxxxx>
> Sent: 2022年6月16日 7:16
> To: Hongxing Zhu <hongxing.zhu@xxxxxxx>; Lucas Stach
> <l.stach@xxxxxxxxxxxxxx>; Rob Herring <robh+dt@xxxxxxxxxx>; Mark Brown
> <broonie@xxxxxxxxxx>; Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>; Fabio
> Estevam <festevam@xxxxxxxxx>; Francesco Dolcini
> <francesco.dolcini@xxxxxxxxxxx>
> Cc: linux-pci@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx;
> linux-kernel@xxxxxxxxxxxxxxx; kernel@xxxxxxxxxxxxxx; dl-linux-imx
> <linux-imx@xxxxxxx>; Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
> Subject: [PATCH v12 03/13] PCI: imx6: Move imx6_pcie_enable_ref_clk()
> earlier
>
> From: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
>
> Move imx6_pcie_enable_ref_clk() earlier so it's not in the middle between
> imx6_pcie_assert_core_reset() and imx6_pcie_deassert_core_reset(). No
> functional change intended.
>
> Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
Acked-by: Richard Zhu <hongxing.zhu@xxxxxxx>
Best Regards
Richard Zhu
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 96 +++++++++++++--------------
> 1 file changed, 48 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> b/drivers/pci/controller/dwc/pci-imx6.c
> index e63eb6380020..a6d2b907d42b 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -520,54 +520,6 @@ static int imx6_pcie_attach_pd(struct device *dev)
> return 0;
> }
>
> -static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) -{
> - struct device *dev = imx6_pcie->pci->dev;
> -
> - switch (imx6_pcie->drvdata->variant) {
> - case IMX7D:
> - case IMX8MQ:
> - reset_control_assert(imx6_pcie->pciephy_reset);
> - fallthrough;
> - case IMX8MM:
> - reset_control_assert(imx6_pcie->apps_reset);
> - break;
> - case IMX6SX:
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> - IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
> - IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
> - /* Force PCIe PHY reset */
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
> - IMX6SX_GPR5_PCIE_BTNRST_RESET,
> - IMX6SX_GPR5_PCIE_BTNRST_RESET);
> - break;
> - case IMX6QP:
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_SW_RST,
> - IMX6Q_GPR1_PCIE_SW_RST);
> - break;
> - case IMX6Q:
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
> - break;
> - }
> -
> - if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
> - int ret = regulator_disable(imx6_pcie->vpcie);
> -
> - if (ret)
> - dev_err(dev, "failed to disable vpcie regulator: %d\n",
> - ret);
> - }
> -
> - /* Some boards don't have PCIe reset GPIO. */
> - if (gpio_is_valid(imx6_pcie->reset_gpio))
> - gpio_set_value_cansleep(imx6_pcie->reset_gpio,
> - imx6_pcie->gpio_active_high);
> -}
> -
> static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) {
> struct dw_pcie *pci = imx6_pcie->pci;
> @@ -628,6 +580,54 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie
> *imx6_pcie)
> return ret;
> }
>
> +static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) {
> + struct device *dev = imx6_pcie->pci->dev;
> +
> + switch (imx6_pcie->drvdata->variant) {
> + case IMX7D:
> + case IMX8MQ:
> + reset_control_assert(imx6_pcie->pciephy_reset);
> + fallthrough;
> + case IMX8MM:
> + reset_control_assert(imx6_pcie->apps_reset);
> + break;
> + case IMX6SX:
> + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> + IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
> + IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
> + /* Force PCIe PHY reset */
> + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
> + IMX6SX_GPR5_PCIE_BTNRST_RESET,
> + IMX6SX_GPR5_PCIE_BTNRST_RESET);
> + break;
> + case IMX6QP:
> + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + IMX6Q_GPR1_PCIE_SW_RST,
> + IMX6Q_GPR1_PCIE_SW_RST);
> + break;
> + case IMX6Q:
> + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
> + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
> + break;
> + }
> +
> + if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
> + int ret = regulator_disable(imx6_pcie->vpcie);
> +
> + if (ret)
> + dev_err(dev, "failed to disable vpcie regulator: %d\n",
> + ret);
> + }
> +
> + /* Some boards don't have PCIe reset GPIO. */
> + if (gpio_is_valid(imx6_pcie->reset_gpio))
> + gpio_set_value_cansleep(imx6_pcie->reset_gpio,
> + imx6_pcie->gpio_active_high);
> +}
> +
> static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) {
> struct dw_pcie *pci = imx6_pcie->pci;
> --
> 2.25.1
