On Fri, 10 Jun 2022 11:56:54 +0300, Serge Semin wrote: > In accordance with [1] the CX_NFUNC IP-core synthesize parameter is > responsible for the number of physical functions to support in the EP > mode. Its upper limit is 32. Let's use it to constrain the number of > PCIe functions the DW PCIe EP DT-nodes can advertise. > > [1] Synopsys DesignWare Cores PCI Express Controller Databook - DWC PCIe > Endpoint, Version 5.40a, March 2019, p. 887. > > Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> > > --- > > Changelog v3: > - This is a new patch unpinned from the next one: > https://lore.kernel.org/linux-pci/20220503214638.1895-2-Sergey.Semin@xxxxxxxxxxxxxxxxxxxx/ > by the Rob' request. (@Rob) > --- > Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
