On Fri, Nov 11, 2011 at 4:37 PM, David Woodhouse <dwmw2@xxxxxxxxxxxxx> wrote: > This brain-damage only affects the first chipsets > from before we worked out that cache incoherency was a *really* f*cking > stupid idea, doesn't it? As we talked about at KS, I have some Westmere EP (ie latest and greatest server platform) systems where the BIOS exposes an option that allows choosing VT-d coherency on or off, and defaults it to "off". What is the "official" Intel line on coherency with Westmere and Tylersburg -- because as I also mentioned, I was seeing some problems with VT-d and the default "coherency off" setting that looked like the IOMMU HW is getting stale PTEs (ie a missing or not working cache flush). - R. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
