RE: [PATCH v4 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



> 
> On Thu, Jun 09, 2022 at 09:59:08AM +0200, Michal Simek wrote:
> > On 6/8/22 21:14, Bjorn Helgaas wrote:
> > > On Wed, Jun 08, 2022 at 10:10:46PM +0530, Bharat Kumar Gogada wrote:
> > > > Xilinx Versal Premium series has CPM5 block which supports Root
> > > > Port functioning at Gen5 speed.
> > > >
> > > > Xilinx Versal CPM5 has few changes with existing CPM block.
> > > > - CPM5 has dedicated register space for control and status registers.
> > > > - CPM5 legacy interrupt handling needs additional register bit
> > > >    to enable and handle legacy interrupts.
> > > >
> > > > Signed-off-by: Bharat Kumar Gogada
> > > > <bharat.kumar.gogada@xxxxxxxxxx>
> > > > ---
> > > >   drivers/pci/controller/pcie-xilinx-cpm.c | 33
> +++++++++++++++++++++++-
> > > >   1 file changed, 32 insertions(+), 1 deletion(-)
> > >
> > > Per MAINTAINERS, xilinx-cpm lacks a maintainer.  Can we get one?
> >
> > Bharat should become maintainer for this driver.
> >
> > My fragment should cover xilinx things in general in case Bharat is
> > not available.
> 
> Great!  Can one of you post a patch to show exactly what you have in mind?
> 
Thanks,  will send patch.

Regards,
Bharat




[Index of Archives]     [DMA Engine]     [Linux Coverity]     [Linux USB]     [Video for Linux]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]     [Greybus]

  Powered by Linux