That flag is set if there is an outbound iATU window used for both PCIe
peripheral config-space accesses and IO ports transfers. Since the flag
semantic is purely Root Port specific, it's unused in neither the DW PCIe
common code nor the DW PCIe Endpoint driver we can freely move it to the
DW PCIe Root Port descriptor. Thus the pcie_port structure will be more
coherent.
Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
---
Changelog v4:
- This is a new patch created on the v4 lap of the series.
---
drivers/pci/controller/dwc/pcie-designware-host.c | 6 +++---
drivers/pci/controller/dwc/pcie-designware.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index f57f456aa543..9da600b841a7 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -491,7 +491,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
ret = pci_generic_config_read(bus, devfn, where, size, val);
- if (!ret && pci->io_cfg_atu_shared)
+ if (!ret && pp->cfg0_io_shared)
dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
pp->io_bus_addr, pp->io_size);
@@ -507,7 +507,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
ret = pci_generic_config_write(bus, devfn, where, size, val);
- if (!ret && pci->io_cfg_atu_shared)
+ if (!ret && pp->cfg0_io_shared)
dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
pp->io_bus_addr, pp->io_size);
@@ -626,7 +626,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
PCIE_ATU_TYPE_IO, pp->io_base,
pp->io_bus_addr, pp->io_size);
else
- pci->io_cfg_atu_shared = true;
+ pp->cfg0_io_shared = true;
}
if (pci->num_ob_windows <= atu_idx)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 8ba239292634..13bffa3eaed6 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -179,6 +179,7 @@ struct dw_pcie_host_ops {
struct pcie_port {
bool has_msi_ctrl:1;
+ bool cfg0_io_shared:1;
u64 cfg0_base;
void __iomem *va_cfg0_base;
u32 cfg0_size;
@@ -274,7 +275,6 @@ struct dw_pcie {
int link_gen;
u8 n_fts[2];
bool iatu_unroll_enabled: 1;
- bool io_cfg_atu_shared: 1;
};
#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
--
2.35.1
