在2022年6月2日六月 下午5:20，Bjorn Helgaas写道：. > > I'd really like to have a single implementation of whatever quirk > works around this. I don't think we should have multiple copies just > because we assume some firmware takes care of part of this for us. > Yeah that was my idea when I was writing the present version of workaround. However in later LS7A revisions Loongson somehow raised MRRS for several PCIe controllers on chip to 1024 and other ports remains to be 256. Kernel have no way to aware of this change and we can only rely on firmware to set proper value. I have no idea how Loongson achieved this in hardware. All those PCIe controllers are attached under the same AXI bus should share the same AXI to HyperTransport bridge as AXI slave behind a bus matrix. Perhaps instead of fixing error handling of their AXI protocol implementation they just increased the buffer size in AXI bridge so it can accomplish larger requests at one time. >> In keystone’s case it’s likely that their firmware won’t do such thing, so >> their workaround shouldn’t be removed. >> And no_inc_mrrs should be set for them to prevent device drivers modifying >> MRRS afterwards. > > I have the vague impression that this issue is related to an arm64 AXI > bus property [2] or maybe a DesignWare controller property [3], so > this might affect several PCIe controller drivers. In my understanding it’s likely to be a AXI implementation issue. Thanks > >> > Whatever we do should be as uniform as possible across host >> > controllers. >> > >> > [1] >> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/dwc/pci-keystone.c?id=v5.18#n528 > > [2] https://lore.kernel.org/all/20211126083119.16570-4-kishon@xxxxxx/ > [3] https://lore.kernel.org/all/m3r1f08p83.fsf@xxxxxxxxxxx/ -- - Jiaxun
