On 6/2/2022 1:59 PM, Manivannan Sadhasivam wrote:
On Wed, Jun 01, 2022 at 05:57:53PM +0530, Krishna Chaitanya Chundru wrote:
[+cc kenny, vidya]
On 6/1/2022 5:53 PM, Krishna chaitanya chundru wrote:
In ASPM driver, LTR threshold scale and value is updating based on
s/is/are
s/updating/updated
tcommon_mode and t_poweron values. In kioxia NVMe L1.2 is failing due to
LTR threshold scale and value is greater values than max snoop/non-snoop
s/is/are
value.
Based on PCIe r4.1, sec 5.5.1, L1.2 substate must be entered when
reported snoop/no-snoop values is greather than or equal to
LTR_L1.2_THRESHOLD value.
Suggested-by: Prasad Malisetty <quic_pmaliset@xxxxxxxxxxx>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx>
If you are inheriting the patch from Prasad, then you should still give the
authorship to him (unless the patch has changed significantly). You can add
your S-o-b tag to convey that you are carrying the patch from him.
Thanks mani for pointing this, I will modify this in next patch.
---
I am takking this patch forward as prasad is no more working with our org.
Changes since v2:
- Replaced LTRME logic with max snoop/no-snoop latencies check.
Changes since v1:
- Added missing variable declaration in v1 patch
---
drivers/pci/pcie/aspm.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index a96b742..4a15e50 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -465,10 +465,19 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
u32 ctl1 = 0, ctl2 = 0;
u32 pctl1, pctl2, cctl1, cctl2;
u32 pl1_2_enables, cl1_2_enables;
+ int ltr;
This could be u16 too.
Will change in the next patch
+ u16 max_snoop_lat = 0, max_nosnoop_lat = 0;
No need to initialize these variables.
I will update these in next patch.
if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
return;
+ ltr = pci_find_ext_capability(child, PCI_EXT_CAP_ID_LTR);
+ if (!ltr)
+ return;
Is this capability implemented always?
Based up on spec 4.1, sec 5.5 Ports that support the L1.2 substate for
ASPM L1 must support this.
And there is already a check in this function if there is no L1.2
support the function is returning.
+
+ pci_read_config_word(child, ltr + PCI_LTR_MAX_SNOOP_LAT, &max_snoop_lat);
+ pci_read_config_word(child, ltr + PCI_LTR_MAX_NOSNOOP_LAT, &max_nosnoop_lat);
+
/* Choose the greater of the two Port Common_Mode_Restore_Times */
val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
@@ -501,7 +510,18 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
*/
l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
encode_l12_threshold(l1_2_threshold, &scale, &value);
- ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
+
+ /*
+ * If the max snoop and no snoop latencies are '0', then avoid updating scale
+ * and value.
+ *
This looks fine but...
+ * Based on PCIe r4.1, sec 5.5.1, L1.2 substate must be entered when reported
+ * snoop/no-snoop values is greather than or equal to LTR_L1.2_THRESHOLD value.
s/is/are
What about this? What if the snoop/nosnoop latencies are not equal to zero and
lower than LTR_L1.2_THRESHOLD?
Thanks,
Mani
Will address this in next patch.
Thanks,
Krishna Chaitanya.
+ */
+ if ((max_snoop_lat == 0) && (max_nosnoop_lat == 0))
+ ctl1 |= t_common_mode << 8;
+ else
+ ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
/* Some broken devices only support dword access to L1 SS */
pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1);
