From: Ira Weiny <ira.weiny@xxxxxxxxx>
Each CXL device may have multiple DOE mailbox capabilities and each
mailbox may support multiple protocols. CXL port devices need to query
the CDAT information specifically.
Search the DOE mailboxes for one which supports the CDAT protocol.
Cache that mailbox to be used for future queries.
Only support memory devices at this time.
Signed-off-by: Ira Weiny <ira.weiny@xxxxxxxxx>
---
Changes from V8
Incorporate feedback from Jonathan
Move all this to the cxl_port object
Changes from V7
Minor code clean ups
Changes from V6
Adjust for aux devices being a CXL only concept
Update commit msg.
Ensure devices iterated by auxiliary_find_device() are checked
to be DOE devices prior to checking for the CDAT
protocol
From Ben
Ensure reference from auxiliary_find_device() is dropped
---
drivers/cxl/core/pci.c | 28 ++++++++++++++++++++++++++++
drivers/cxl/core/port.c | 2 ++
drivers/cxl/cxl.h | 2 ++
drivers/cxl/cxlpci.h | 1 +
4 files changed, 33 insertions(+)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index c4c99ff7b55e..5497a65bdcf3 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -4,11 +4,14 @@
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/pci.h>
+#include <linux/pci-doe.h>
#include <cxlpci.h>
#include <cxlmem.h>
#include <cxl.h>
#include "core.h"
+#define CXL_DOE_PROTOCOL_TABLE_ACCESS 2
+
/**
* DOC: cxl core pci
*
@@ -458,3 +461,28 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm)
return 0;
}
EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);
+
+void cxl_find_cdat_mb(struct cxl_port *port)
+{
+ struct device *dev = port->uport;
+ struct cxl_memdev *cxlmd;
+ struct cxl_dev_state *cxlds;
+ int i;
+
+ if (!is_cxl_memdev(dev))
+ return;
+
+ cxlmd = to_cxl_memdev(dev);
+ cxlds = cxlmd->cxlds;
+
+ for (i = 0; i < cxlds->num_mbs; i++) {
+ struct pci_doe_mb *cur = cxlds->doe_mbs[i];
+
+ if (pci_doe_supports_prot(cur, PCI_DVSEC_VENDOR_ID_CXL,
+ CXL_DOE_PROTOCOL_TABLE_ACCESS)) {
+ port->cdat_mb = cur;
+ return;
+ }
+ }
+}
+EXPORT_SYMBOL_NS_GPL(cxl_find_cdat_mb, CXL);
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index ea60abda6500..2e2bd65c1024 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -461,6 +461,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
if (IS_ERR(port))
return port;
+ cxl_find_cdat_mb(port);
+
dev = &port->dev;
if (is_cxl_memdev(uport))
rc = dev_set_name(dev, "endpoint%d", port->id);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 140dc3278cde..0a86be589ffc 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -267,6 +267,7 @@ struct cxl_nvdimm {
* @component_reg_phys: component register capability base address (optional)
* @dead: last ep has been removed, force port re-creation
* @depth: How deep this port is relative to the root. depth 0 is the root.
+ * @cdat_mb: Mailbox which supports the CDAT protocol
*/
struct cxl_port {
struct device dev;
@@ -278,6 +279,7 @@ struct cxl_port {
resource_size_t component_reg_phys;
bool dead;
unsigned int depth;
+ struct pci_doe_mb *cdat_mb;
};
/**
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index fce1c11729c2..366b21bd1a01 100644
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -74,4 +74,5 @@ static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
int devm_cxl_port_enumerate_dports(struct cxl_port *port);
struct cxl_dev_state;
int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
+void cxl_find_cdat_mb(struct cxl_port *port);
#endif /* __CXL_PCI_H__ */
--
2.35.1
