On 23/05/2022 11:54, Johan Hovold wrote:
On Sat, May 21, 2022 at 03:53:35AM +0300, Dmitry Baryshkov wrote:
PCIe pipe clk (and some other clocks) must be parked to the "safe"
source (bi_tcxo) when corresponding GDSC is turned off and on again.
Currently this is handcoded in the PCIe driver by reparenting the
gcc_pipe_N_clk_src clock.
Instead of doing it manually, follow the approach used by
clk_rcg2_shared_ops and implement this parking in the enable() and
disable() clock operations for respective pipe clocks.
Changes since v7:
- Brought back the struct clk_regmap_phy_mux (Johan)
- Fixed includes (Stephen)
So this is v8, but Subject still reads v7.
It looks like you also dropped the CLK_SET_RATE_PARENT flags in this
version.
Yes. It was not there originally. And I don't think we really set the
rate for the pipe clock (and support setting it for the phy's pipe output).
For the series:
Reviewed-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
Tested-by: Reviewed-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
Johan
--
With best wishes
Dmitry
