On Wed, May 04, 2022 at 12:46:33AM +0300, Serge Semin wrote: > Depending on the DWC PCIe RC/EP/DM IP-core configuration parameters the > controllers can be equipped not only with various number of inbound and > outbound iATU windows, but with varied regions settings like alignment > (which is also the minimum window size), minimum and maximum sizes. So to > speak if internal ATU is enabled for the denoted IP-cores then the former > settings will be defined by the CX_ATU_MIN_REGION_SIZE parameter while the > later one will be determined by the CX_ATU_MAX_REGION_SIZE configuration > parameter. Anyway having these parameters used in the driver will help to > verify whether the requested inbound or outbound memory mappings can be > fully created. Currently the driver doesn't perform any corresponding > checking. > > Note 1. The extended iATU regions have been supported since DWC PCIe > v4.60a. There is no need in testing the upper limit register availability > for the older cores. > > Note 2. The regions alignment is determined with using the fls() method > since the lower four bits of the ATU Limit register can be occupied with > the Circular Buffer Increment setting, which can be initialized with > zeros. > > The (dma-)ranges verification will be added a bit later in one of the next > commits. > > Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> > --- > drivers/pci/controller/dwc/pcie-designware.c | 33 +++++++++++++++++--- > drivers/pci/controller/dwc/pcie-designware.h | 2 ++ > 2 files changed, 31 insertions(+), 4 deletions(-) Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
