On 13/05/2022 15:42, Johan Hovold wrote:
On Thu, May 12, 2022 at 01:45:42PM +0300, Dmitry Baryshkov wrote:
On some of Qualcomm platforms each group of 32 MSI vectors is routed to the
separate GIC interrupt. Thus, to receive higher MSI vectors properly,
declare that the host should use split MSI IRQ handling on these
platforms.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 2e5464edc36e..f79752d1d680 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -194,6 +194,7 @@ struct qcom_pcie_ops {
struct qcom_pcie_cfg {
const struct qcom_pcie_ops *ops;
+ unsigned int has_split_msi_irq:1;
unsigned int pipe_clk_need_muxing:1;
unsigned int has_tbu_clk:1;
unsigned int has_ddrss_sf_tbu_clk:1;
@@ -1592,6 +1599,11 @@ static int qcom_pcie_probe(struct platform_device *pdev)
pcie->cfg = pcie_cfg;
+ if (pcie->cfg->has_split_msi_irq) {
+ pp->num_vectors = MAX_MSI_IRQS;
+ pp->has_split_msi_irq = true;
+ }
If all qcom platform that can support more than 32 MSI require multiple
IRQs, how about adding num_vectors to the config instead and set
pp->has_split_msi_irq when cfg->num_vectors is set (or unconditionally
if you remove the corresponding warning you just added to the dwc host
code)?
At least some sc8280xp seem to only support 128 MSI (using 4 IRQs).
Nice idea, let's do this.
+
pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
if (IS_ERR(pcie->reset)) {
ret = PTR_ERR(pcie->reset);
Johan
--
With best wishes
Dmitry
