On Wed, May 11, 2022 at 09:13:45PM +0200, Lukas Wunner wrote: > When an IDE-capable device is runtime suspended to D3hot and later > runtime resumed to D0, it may not preserve its internal state. > (The No_Soft_Reset bit in the Power Management Control/Status Register > tells us whether the device is capable of preserving internal state > over a transition to D3hot, see PCIe r6.0, sec. 7.5.2.2.) > > Likewise, when an IDE-capable device is reset (e.g. due to Downstream > Port Containment, AER or a bus reset initiated by user space), > internal state is lost and must be reconstructed by pci_restore_state(). > That state includes the SPDM session or IDE encryption. Digging a little further, sec. 6.33.8 says that "The No_Soft_Reset bit must be Set", so at least IDE will always survive a D3hot transition. But the reset argument still stands: That same section says that all IDE streams transition to Insecure and all keys are invalidated upon reset. Thanks, Lukas
