Am Mittwoch, 11. Mai 2022, 17:00:05 CEST schrieb Lorenzo Pieralisi:
> On Wed, May 11, 2022 at 10:26:20AM -0400, Peter Geis wrote:
> > On Wed, May 11, 2022 at 9:50 AM Lorenzo Pieralisi
> > <lorenzo.pieralisi@xxxxxxx> wrote:
> > >
> > > On Fri, Apr 29, 2022 at 08:38:28AM -0400, Peter Geis wrote:
> > > > The PCIe controller is in an unknown state at driver probe. This can
> > > > lead to undesireable effects when the driver attempts to configure the
> > > > controller.
> > > >
> > > > Prevent issues in the future by resetting the core during probe.
> > > >
> > > > Signed-off-by: Peter Geis <pgwipeout@xxxxxxxxx>
> > > > Tested-by: Nicolas Frattaroli <frattaroli.nicolas@xxxxxxxxx>
> > > > ---
> > > > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 23 ++++++++-----------
> > > > 1 file changed, 10 insertions(+), 13 deletions(-)
> > >
> > > I fear that the controller reset behaviour is bootloader/firmware
> > > dependent.
> > >
> > > Are we sure we are not triggering any regressions by resetting the
> > > controller in the middle of probe (aka is the driver implicitly
> > > relying on existing behaviour on systems that are not the ones
> > > you are testing on) ?
> > >
> > > Just asking, the rockchip maintainers should be able to answer this
> > > question.
> >
> > This is a new driver with no current users, this series enables the
> > first user. It does not support ACPI nor any sort of handoff at this
> > time.
>
> Ok. I will take patches [1-3], dts changes will have to go via
> platform trees, I hope that's fine.
yep, that sounds great and I'll pick the dts patches then :-)
Thanks
Heiko
> > > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > > > index c9b341e55cbb..faedbd6ebc20 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > > > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > > > @@ -152,6 +152,11 @@ static int rockchip_pcie_resource_get(struct platform_device *pdev,
> > > > if (IS_ERR(rockchip->rst_gpio))
> > > > return PTR_ERR(rockchip->rst_gpio);
> > > >
> > > > + rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
> > > > + if (IS_ERR(rockchip->rst))
> > > > + return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst),
> > > > + "failed to get reset lines\n");
> > > > +
> > > > return 0;
> > > > }
> > > >
> > > > @@ -182,18 +187,6 @@ static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip)
> > > > phy_power_off(rockchip->phy);
> > > > }
> > > >
> > > > -static int rockchip_pcie_reset_control_release(struct rockchip_pcie *rockchip)
> > > > -{
> > > > - struct device *dev = rockchip->pci.dev;
> > > > -
> > > > - rockchip->rst = devm_reset_control_array_get_exclusive(dev);
> > > > - if (IS_ERR(rockchip->rst))
> > > > - return dev_err_probe(dev, PTR_ERR(rockchip->rst),
> > > > - "failed to get reset lines\n");
> > > > -
> > > > - return reset_control_deassert(rockchip->rst);
> > > > -}
> > > > -
> > > > static const struct dw_pcie_ops dw_pcie_ops = {
> > > > .link_up = rockchip_pcie_link_up,
> > > > .start_link = rockchip_pcie_start_link,
> > > > @@ -222,6 +215,10 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
> > > > if (ret)
> > > > return ret;
> > > >
> > > > + ret = reset_control_assert(rockchip->rst);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > /* DON'T MOVE ME: must be enable before PHY init */
> > > > rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
> > > > if (IS_ERR(rockchip->vpcie3v3)) {
> > > > @@ -241,7 +238,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
> > > > if (ret)
> > > > goto disable_regulator;
> > > >
> > > > - ret = rockchip_pcie_reset_control_release(rockchip);
> > > > + ret = reset_control_deassert(rockchip->rst);
> > > > if (ret)
> > > > goto deinit_phy;
> > > >
> > > > --
> > > > 2.25.1
> > > >
>
