From: Jeffrey Hugo <quic_jhugo@xxxxxxxxxxx> Sent: Monday, May 9, 2022 2:48 PM > > While multi-MSI appears to work with pci-hyperv.c, there was a concern about > how linux was doing the ITRE allocations. Patch 2 addresses the concern. > > However, patch 2 exposed an issue with how compose_msi_msg() was freeing a > previous allocation when called for the Nth time. Imagine a driver using > pci_alloc_irq_vectors() to request 32 MSIs. This would cause compose_msi_msg() > to be called 32 times, once for each MSI. With patch 2, MSI0 would allocate > the ITREs needed, and MSI1-31 would use the cached information. Then the driver > uses request_irq() on MSI1-17. This would call compose_msi_msg() again on those > MSIs, which would again use the cached information. Then unmask() would be > called to retarget the MSIs to the right VCPU vectors. Finally, the driver > calls request_irq() on MSI0. This would call conpose_msi_msg(), which would > free the block of 32 MSIs, and allocate a new block. This would undo the > retarget of MSI1-17, and likely leave those MSIs targeting invalid VCPU vectors. > This is addressed by patch 1, which is introduced first to prevent a regression. > > Jeffrey Hugo (2): > PCI: hv: Reuse existing ITRE allocation in compose_msi_msg() > PCI: hv: Fix interrupt mapping for multi-MSI > > drivers/pci/controller/pci-hyperv.c | 76 ++++++++++++++++++++++++++++--------- > 1 file changed, 59 insertions(+), 17 deletions(-) > > -- > 2.7.4 I tested these two patches in combination with the earlier two on 5.18-rc6 in an ARM64 VM in Azure. This was a smoke-test to ensure everything compiled and that the changes aren't fundamentally broken on ARM64. The PCI device in this case is the Mellanox Virtual Function offered to VMs in Azure, which is MSI-X. As such, the new MSI "batch" handling is not tested. Tested-by: Michael Kelley <mikelley@xxxxxxxxxxxxx>
