On Wed, Apr 27 2022 at 19:35, Thomas Gleixner wrote:
> On Wed, Apr 27 2022 at 09:59, Salvatore Bonaccorso wrote:
> XEN guests do not use the common PCI mask/unmask machinery which would
> unmask the interrupt on request_irq().
>
> So I assume that the following happens:
>
> Guest Hypervisor
>
> msix_capabilities_init()
> ....
> alloc_irq()
> xen_magic() -> alloc_msix_interrupt()
> request_irq()
>
> msix_mask_all() -> trap
> do_magic()
> request_irq()
> unmask()
> xen_magic()
> unmask_evtchn() -> do_more_magic()
>
> So I assume further that msix_mask_all() actually is able to mask the
> interrupts in the hardware (ctrl word of the vector table) despite the
> hypervisor having allocated and requested the interrupt already.
>
> Nothing in XEN_HVM handles PCI/MSI[-X] mask/unmask in the guest, so I
> really have to ask why XEN_HVM does not disable PCI/MSI[-X] masking like
> XEN_PV does. I can only assume the answer is voodoo...
>
> Maybe the XEN people have some more enlightened answers to that.
So I was talking to Juergen about this and he agrees, that for the case
where a XEN HVM guest uses the PIRQ/Eventchannel mechanism PCI/MSI[-X]
masking should be disabled like it is done for XEN PV.
Why the hypervisor grants the mask write is still mysterious, but I
leave that to the folks who can master the XEN voodoo.
I'll send out a patch in minute.
Thanks,
tglx
