Hi Geert, On Wed, 27 Apr 2022 17:15:15 +0200 Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > Hi Hervé, > > On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@xxxxxxxxxxx> wrote: > > Add internal PCI bridge support for the r9a06g032 SOC. The Renesas > > RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one > > present in the R-Car Gen2 family. > > Compared to the R-Car Gen2 family, it needs three clocks instead of > > one. > > > > Signed-off-by: Herve Codina <herve.codina@xxxxxxxxxxx> > > Thanks for your patch! > > > --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml > > +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml > > @@ -113,6 +113,37 @@ required: > > - "#size-cells" > > - "#interrupt-cells" > > > > +if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - renesas,pci-rzn1 > > + > > +then: > > + properties: > > + clocks: > > + items: > > + - description: Internal bus clock (AHB) for HOST > > + - description: Internal bus clock (AHB) Power Management > > + - description: PCI clock for USB subsystem > > + clock-names: > > + items: > > + - const: hclk_usbh > > + - const: hclk_usbpm > > + - const: clk_pci_usb > > These are the provider names. > I think they should use the consumer names: usb_hclkh, usb_hclkpm, > and usb_pciclk. Yes, it makes sense. I will changed in v4. > > The rest looks good to me. Perfect. Thanks for the review, Hervé -- Hervé Codina, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
