On Fri, Mar 25, 2022 at 11:40:42PM +0530, Manivannan Sadhasivam wrote:
> On Thu, Mar 24, 2022 at 04:48:34AM +0300, Serge Semin wrote:
> > DW eDMA doesn't perform any translation of the traffic generated on the
> > CPU/Application side. It just generates read/write AXI-bus requests with
> > the specified addresses. But in case if the dma-ranges DT-property is
> > specified for a platform device node, Linux will use it to map the CPU
> > memory regions into the DMAable bus ranges. This isn't what we want for
> > the eDMA embedded into the locally accessed DW PCIe Root Port and
> > End-point. In order to work that around let's set the chan_dma_dev flag
> > for each DW eDMA channel thus forcing the client drivers to getting a
> > custom dma-ranges-less parental device for the mappings.
> >
> > Note it will only work for the client drivers using the
> > dmaengine_get_dma_device() method to get the parental DMA device.
> >
> > Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
> > ---
> > drivers/dma/dw-edma/dw-edma-core.c | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c
> > index 72a51970bfba..ca5cd7c99571 100644
> > --- a/drivers/dma/dw-edma/dw-edma-core.c
> > +++ b/drivers/dma/dw-edma/dw-edma-core.c
> > @@ -716,6 +716,21 @@ static int dw_edma_alloc_chan_resources(struct dma_chan *dchan)
> > if (chan->status != EDMA_ST_IDLE)
> > return -EBUSY;
> >
> > + /* Bypass the dma-ranges based memory regions mapping since the
> > + * inbound iATU only affects the traffic incoming from the
> > + * PCIe bus.
> > + */
>
> Bypass the dma-ranges based memory regions mapping since eDMA doesn't do any
> address translation for the CPU address?
Seems reasonable. I'll fix the comment to being clearer.
BTW since we omit setting the DMA_BYPASS flag of the outbound iATU
windows, the DMA address is actually affected by the DW PCIe
controller but in a bit of a sophisticated way. AFAIU if no DMA_BYPASS
flag specified and the resultant TLP address falls into any outbound
iATU window, the address will be translated in accordance with that
window translation rule. So happen the chains like this:
+ DMA write:
CPU memory <-,-> eDMA LLi:SAR(CPU address, data) -> eDMA LLi:DAR(DMA address, data) ->
Outbound iATU TLP MWr(PCIe address, data) -> PCIe memory.
+ DMA read:
eDMA SAR(DMA address, ?) -> Outbound iATU TLP MRd(PCIe address, ?) ->
PCIe memory -> Outbound iATU TLP MRd(PCIe address, data) -> eDMA
SAR(DMA address, data) -> eDMA DAR(CPU address, data) -> CPU memory
Due to that handy feature we don't need to search for the PCIe bus
memory range matching the passed source and destination DMA addresses
of the SG-lists. It is done by the Outbound iATU engine automatically.
If the DMA_BYPASS flag was set, all the Outbound iATU-related stages
would have been omitted from the diagram above and the DMA<->PCIe
translations would have needed to be performed in the eDMA driver
code.
-Sergey
>
> Other than this,
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
>
> Thanks,
> Mani
>
> > + if (chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) {
> > + dchan->dev->chan_dma_dev = true;
> > +
> > + dchan->dev->device.dma_coherent = chan->dw->chip->dev->dma_coherent;
> > + dma_coerce_mask_and_coherent(&dchan->dev->device,
> > + dma_get_mask(chan->dw->chip->dev));
> > + dchan->dev->device.dma_parms = chan->dw->chip->dev->dma_parms;
> > + } else {
> > + dchan->dev->chan_dma_dev = false;
> > + }
> > +
> > pm_runtime_get(chan->dw->chip->dev);
> >
> > return 0;
> > --
> > 2.35.1
> >
