[ Please trim your replies. ] On Wed, Apr 13, 2022 at 08:57:47PM +0300, Dmitry Baryshkov wrote: > On 13/04/2022 12:15, Johan Hovold wrote: > > On Tue, Apr 12, 2022 at 10:38:35PM +0300, Dmitry Baryshkov wrote: > >> On recent Qualcomm platforms the QMP PIPE clocks feed into a set of > >> muxes which must be parked to the "safe" source (bi_tcxo) when > >> corresponding GDSC is turned off and on again. Currently this is > >> handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src > >> clock. However the same code sequence should be applied in the > >> pcie-qcom endpoint, USB3 and UFS drivers. > > > > I'm starting to think this really belongs in the PHY driver which is the > > provider of the pipe clock. Moving it there would also allow the code to > > be shared between PCIe, USB, and UFS. > > > > The PHY driver enables the pipe clock by starting the PHY and before > > doing so there's no point in updating the mux. Similarly, the PHY driver > > can restore the "safe" source after disabling the pipe clock. > > I thought about this at some point. However it would still mean that the > driver does the dance manually: disable pipe_clock, switch parent, > sleep, switch the parent back, enable pipe clock. Switching parents is > tied to disabling pipe_clock, so enforcing this link seems like a better > option to me. No, that's precisely my point. It is not tied to disabling (gating) the pipe clock, it is tied to powering down the PHY (i.e. disabling the pipe clock source). And that is under the control of the PHY driver. In practise, once we've cleaned up the other users of the pipe clock, tying it to pipe clock disabling will work, but it doesn't prevent anyone from shooting themselves in the foot as the "safe-mux" name suggests (i.e. it is still possibly to enable the pipe clock while its source is disabled). > No to mention that it would complicate already overcomplicated QMP driver. That driver sure could use some love, but that's not a valid argument against adding things were they belong. And regarding complexity, I have a working prototype implementation here which is smaller than what you're proposing and very straight forward. > > That way there's no magic happening behind scenes, the clock framework > > always reports the actual state of the tree, and the reason for all of > > this can be documented in the QMP PHY driver once and for all. > > We already have such 'magic' for the RCG2 (clk_rcg2_shared_ops), with > the very practical reason. If the clock is running from the tcxo, it is > as good as disabled from the practical purpose. That implementation doesn't try to implement the caching you're proposing and hence doesn't suffer from the associated implementation issues. > > The only change to the bindings compared to what this series proposes is > > that the PHY driver also needs a reference to bi_tcxo. > > And this looks as bad, as providing bi_tcxo to the PCI device. From the > schematics/silicon point of view neither of them actually uses these > parents. Neither of them uses the pipe_clock_src. What do they need is > just the pipe_clock. The rest should be in the programming API. No, the PHY driver is both the provider of the source clock for the pipe clock and the consumer of the latter. That it may need to handle any muxes in between the two only makes sense. Hiding this away and spreading the implementation out over multiple clock drivers (i.e. every mux definition for each platform + the regmap-mux hack) only obscures things. Johan
