On recent Qualcomm platforms the QMP PIPE clocks feed into a set of
muxes which must be parked to the "safe" source (bi_tcxo) when
corresponding GDSC is turned off and on again. Currently this is
handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src
clock. However the same code sequence should be applied in the
pcie-qcom endpoint, USB3 and UFS drivers.
Rather than copying this sequence over and over again, follow the
example of clk_rcg2_shared_ops and implement this parking in the
enable() and disable() clock operations. As we are changing the parent
behind the back of the clock framework, also implement custom
set_parent() and get_parent() operations behaving accroding to the clock
framework expectations (cache the new parent if the clock is in disabled
state, return cached parent).
Reviewed-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
drivers/clk/qcom/clk-regmap-mux.c | 121 ++++++++++++++++++++++++++++++
drivers/clk/qcom/clk-regmap-mux.h | 3 +
2 files changed, 124 insertions(+)
diff --git a/drivers/clk/qcom/clk-regmap-mux.c b/drivers/clk/qcom/clk-regmap-mux.c
index 45d9cca28064..fe61a9248f2f 100644
--- a/drivers/clk/qcom/clk-regmap-mux.c
+++ b/drivers/clk/qcom/clk-regmap-mux.c
@@ -49,9 +49,130 @@ static int mux_set_parent(struct clk_hw *hw, u8 index)
return regmap_update_bits(clkr->regmap, mux->reg, mask, val);
}
+static u8 mux_safe_get_parent(struct clk_hw *hw)
+{
+ struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
+ unsigned int val;
+
+ if (clk_hw_is_enabled(hw))
+ return mux_get_parent(hw);
+
+ val = mux->stored_parent;
+
+ if (mux->parent_map)
+ return qcom_find_src_index(hw, mux->parent_map, val);
+
+ return val;
+}
+
+static int mux_safe_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
+
+ if (clk_hw_is_enabled(hw))
+ return mux_set_parent(hw, index);
+
+ if (mux->parent_map)
+ index = mux->parent_map[index].src;
+
+ mux->stored_parent = index;
+
+ return 0;
+}
+
+static int mux_safe_is_enabled(struct clk_hw *hw)
+{
+ struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
+ struct clk_regmap *clkr = to_clk_regmap(hw);
+ unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
+ unsigned int val;
+
+ regmap_read(clkr->regmap, mux->reg, &val);
+ val = (val & mask) >> mux->shift;
+
+ if (mux->parent_map) {
+ int src;
+
+ src = qcom_map_cfg_src(hw, mux->parent_map, val);
+ if (WARN_ON(src < 0))
+ return true;
+
+ return (unsigned int)src != mux->safe_src_parent;
+ }
+
+ return val != mux->safe_src_parent;
+}
+
+static void mux_safe_disable(struct clk_hw *hw)
+{
+ struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
+ struct clk_regmap *clkr = to_clk_regmap(hw);
+ unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
+ unsigned int val;
+
+ regmap_read(clkr->regmap, mux->reg, &val);
+
+ val = (val & mask) >> mux->shift;
+ if (mux->parent_map) {
+ int src, cfg;
+
+ src = qcom_map_cfg_src(hw, mux->parent_map, val);
+ if (WARN_ON(src < 0))
+ return;
+
+ mux->stored_parent = src;
+
+ cfg = qcom_map_src_cfg(hw, mux->parent_map, mux->safe_src_parent);
+ if (WARN_ON(cfg < 0))
+ return;
+
+ val = cfg;
+ } else {
+ mux->stored_parent = val;
+
+ val = mux->safe_src_parent;
+ }
+
+ val <<= mux->shift;
+
+ regmap_update_bits(clkr->regmap, mux->reg, mask, val);
+}
+
+static int mux_safe_enable(struct clk_hw *hw)
+{
+ struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
+ struct clk_regmap *clkr = to_clk_regmap(hw);
+ unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
+ unsigned int val;
+
+ val = mux->stored_parent;
+ if (mux->parent_map) {
+ int cfg;
+
+ cfg = qcom_map_src_cfg(hw, mux->parent_map, val);
+ if (WARN_ON(cfg < 0))
+ return -EINVAL;
+
+ val = mux->parent_map[cfg].cfg;
+ }
+ val <<= mux->shift;
+
+ return regmap_update_bits(clkr->regmap, mux->reg, mask, val);
+}
+
const struct clk_ops clk_regmap_mux_closest_ops = {
.get_parent = mux_get_parent,
.set_parent = mux_set_parent,
.determine_rate = __clk_mux_determine_rate_closest,
};
EXPORT_SYMBOL_GPL(clk_regmap_mux_closest_ops);
+
+const struct clk_ops clk_regmap_mux_safe_ops = {
+ .enable = mux_safe_enable,
+ .disable = mux_safe_disable,
+ .is_enabled = mux_safe_is_enabled,
+ .get_parent = mux_safe_get_parent,
+ .set_parent = mux_safe_set_parent,
+ .determine_rate = __clk_mux_determine_rate_closest,
+};
+EXPORT_SYMBOL_GPL(clk_regmap_mux_safe_ops);
diff --git a/drivers/clk/qcom/clk-regmap-mux.h b/drivers/clk/qcom/clk-regmap-mux.h
index db6f4cdd9586..6fa5515b583c 100644
--- a/drivers/clk/qcom/clk-regmap-mux.h
+++ b/drivers/clk/qcom/clk-regmap-mux.h
@@ -14,10 +14,13 @@ struct clk_regmap_mux {
u32 reg;
u32 shift;
u32 width;
+ u8 safe_src_parent;
+ u8 stored_parent;
const struct parent_map *parent_map;
struct clk_regmap clkr;
};
extern const struct clk_ops clk_regmap_mux_closest_ops;
+extern const struct clk_ops clk_regmap_mux_safe_ops;
#endif
--
2.35.1
