On Tue, Apr 12, 2022 at 10:54 PM Shawn Lin <shawn.lin@xxxxxxxxxxxxxx> wrote:
>
> Hi Peter,
>
> 在 2022/4/13 2:57, Peter Geis 写道:
> > The legacy interrupts on the rk356x pcie controller are handled by a
> > single muxed interrupt. Add irq domain support to the pcie-dw-rockchip >
> > +static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
> > +{
> > + struct irq_chip *chip = irq_desc_get_chip(desc);
> > + struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
> > + struct device *dev = rockchip->pci.dev;
> > + u32 reg;
> > + u32 hwirq;
> > + u32 virq;
> > +
> > + chained_irq_enter(chip, desc);
> > +
> > + reg = rockchip_pcie_readl_apb(rockchip, 0x8);
> > +
>
>
> Overall it looks good except that 0x8 has a name,
> PCIE_CLIENT_INTR_STATUS_LEGACY. BTW, If you consider adding more support
> to it, for instance, enable/disable/affinity? The downstream kernel
> finished these for better fitting for function driver usage.
Good catch, thanks.
This patch has remained largely unchanged from when I first created it
prior to asking for Rockchip to include support for it in the initial
series.
I would have left it out based on the original counter arguments,
except in testing we have discovered two issues:
A surprising number of cards do not support MSIs.
The current MSI implementation has poor compatibility.
I will look at the downstream implementation and consider possible
changes, but for the time being this does the job.
