On Fri, Mar 25, 2022 at 10:38:25AM +0100, Pali Rohár wrote: > This property specifies slot power limit in mW unit. It is a form-factor > and board specific value and must be initialized by hardware. > > Some PCIe controllers delegate this work to software to allow hardware > flexibility and therefore this property basically specifies what should > host bridge program into PCIe Slot Capabilities registers. > > The property needs to be specified in mW unit instead of the special format > defined by Slot Capabilities (which encodes scaling factor or different > unit). Host drivers should convert the value from mW to needed format. > > Signed-off-by: Pali Rohár <pali@xxxxxxxxxx> > Signed-off-by: Marek Behún <kabel@xxxxxxxxxx> > > --- > This change was already accepted into dt-schema repo by Rob Herring: > https://github.com/devicetree-org/dt-schema/pull/66 Is there a way I can check a DT binding was pulled into the schema without having to read the patch (eg just checking Rob's Acked/Reviewed tags ?) I think this patch should have been posted to devicetree@xxxxxxxxxxxxxxx, by the way. Lorenzo > Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt > index 6a8f2874a24d..b0cc133ed00d 100644 > --- a/Documentation/devicetree/bindings/pci/pci.txt > +++ b/Documentation/devicetree/bindings/pci/pci.txt > @@ -32,6 +32,12 @@ driver implementation may support the following properties: > root port to downstream device and host bridge drivers can do programming > which depends on CLKREQ signal existence. For example, programming root port > not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. > +- slot-power-limit-milliwatt: > + If present, this property specifies slot power limit in milliwatts. Host > + drivers can parse this property and use it for programming Root Port or host > + bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages > + through the Root Port or host bridge when transitioning PCIe link from a > + non-DL_Up Status to a DL_Up Status. > > PCI-PCI Bridge properties > ------------------------- > -- > 2.20.1 >
