Hi Bjorn, On Tue, Apr 05, 2022 at 11:01:51AM -0500, Bjorn Helgaas wrote: > On Tue, Apr 05, 2022 at 12:38:10PM +0300, Mika Westerberg wrote: > > Intel DG2 discrete graphics PCIe endpoints hard-code their acceptable L1 > > ASPM latency to be < 1us even though the hardware actually supports > > higher latencies (> 64 us) just fine. In order to allow the links to go > > into L1 and save power, quirk the acceptable L1 ASPM latency for these > > endpoints to be unlimited. > > Is there a plan to fix this in future DG2 hardware/firmware? > Obviously the point of Dev Cap is to make the device self-describing > so we can avoid updates like this every time new hardware comes out. Yes, I think that's the plan. > > Note this does not have any effect unless the user requested the kernel > > to enable ASPM in the first place (by default we don't enable it). > > I think this depends on the platform and kernel config, doesn't it? > If CONFIG_PCIEASPM_POWERSAVE=y or CONFIG_PCIEASPM_POWER_SUPERSAVE=y > I suspect we would enable ASPM L1 even without the parameters below. > > > This is done with "pcie_aspm=force pcie_aspm.policy=powersupsersave" > > command line parameters. > > s/powersupsersave/powersupersave/ > > This should affect "powersave" as well as "powersupersave", right? > Both enable L1. "powersupersave" enables the L1 substates. > > We *should* be able to enable/disable ASPM L1 using the sysfs "l1_aspm > file, too. Indeed you are right. I think we can drop that paragraph completely from the commit log. Do you want me to send v2 with that corrected or you will do that while applying? Thanks!
