On 28/03/2022 10:43, 이왕석 wrote: > Add description to support Axis, ARTPEC-8 SoC. > ARTPEC-8 is the SoC platform of Axis Communications > and PCIe phy is designed based on SAMSUNG PHY. > > Signed-off-by: Wangseok Lee <wangseok.lee@xxxxxxxxxxx> > --- > .../bindings/phy/axis,artpec8-pcie-phy.yaml | 67 ++++++++++++++++++++++ > 1 file changed, 67 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml > new file mode 100644 > index 0000000..f5f4166 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/axis,artpec8-pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARTPEC-8 SoC PCIe PHY Device Tree Bindings s/Device Tree Bindings// > + > +maintainers: > + - Jesper Nilsson <jesper.nilsson@xxxxxxxx> > + > +properties: > + compatible: > + const: axis,artpec8-pcie-phy > + > + reg: > + items: > + - description: PHY registers. > + - description: PHY coding sublayer registers. > + > + reg-names: > + items: > + - const: phy > + - const: pcs > + > + clocks: > + items: > + - description: PCIe PHY reference clock > + > + clock-names: > + items: > + - const: ref_clk > + > +required: > + - compatible > + - "#phy-cells" > + - reg > + - reg-names > + - clocks > + - clock-names > + - samsung,fsys-sysreg It seems you copied some things from some other bindings, so please clean it up to really fit your device. Best regards, Krzysztof
