> -----Original Message----- > From: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> > Sent: 2022年3月24日 18:05 > To: p.zabel@xxxxxxxxxxxxxx; l.stach@xxxxxxxxxxxxxx; bhelgaas@xxxxxxxxxx; > lorenzo.pieralisi@xxxxxxx; robh@xxxxxxxxxx; shawnguo@xxxxxxxxxx; > vkoul@xxxxxxxxxx; Hongxing Zhu <hongxing.zhu@xxxxxxx> > Cc: linux-phy@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; > linux-pci@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; > linux-kernel@xxxxxxxxxxxxxxx; kernel@xxxxxxxxxxxxxx; dl-linux-imx > <linux-imx@xxxxxxx>; Hongxing Zhu <hongxing.zhu@xxxxxxx> > Subject: Re: (EXT) [PATCH v2 6/7] arm64: dts: imx8mp-evk: Add PCIe support > > Hello Richard, > > thanks for providing PCIe support for iMX8MP. > > Am Montag, 7. März 2022, 10:07:33 CET schrieb Richard Zhu: > > Add PCIe support on i.MX8MP EVK board. > > > > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx> > > --- > > arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 55 > > ++++++++++++++++++++ > > 1 file changed, 55 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > > b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index > > 2eb943210678..ed77455a3f73 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > > @@ -5,6 +5,7 @@ > > > > /dts-v1/; > > > > +#include <dt-bindings/phy/phy-imx8-pcie.h> > > #include "imx8mp.dtsi" > > > > / { > > @@ -33,6 +34,12 @@ memory@40000000 { > > <0x1 0x00000000 0 0xc0000000>; > > }; > > > > + pcie0_refclk: pcie0-refclk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <100000000>; > > + }; > > + > > reg_can1_stby: regulator-can1-stby { > > compatible = "regulator-fixed"; > > regulator-name = "can1-stby"; > > @@ -55,6 +62,17 @@ reg_can2_stby: regulator-can2-stby { > > enable-active-high; > > }; > > > > + reg_pcie0: regulator-pcie { > > + compatible = "regulator-fixed"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_pcie0_reg>; > > + regulator-name = "MPCIE_3V3"; > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + }; > > + > > reg_usdhc2_vmmc: regulator-usdhc2 { > > compatible = "regulator-fixed"; > > pinctrl-names = "default"; > > @@ -297,6 +315,30 @@ pca6416: gpio@20 { > > }; > > }; > > > > +&pcie_phy { > > + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; > > + clocks = <&pcie0_refclk>; > > + clock-names = "ref"; > > + status = "okay"; > > +}; > > + > > +&pcie{ > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_pcie0>; > > + reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; > > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > > + <&clk IMX8MP_CLK_PCIE_ROOT>, > > + <&clk IMX8MP_CLK_HSIO_AXI>; > > + clock-names = "pcie", "pcie_aux", "pcie_bus"; > > This causes the following warnings in dtbs_check (paths stripped): > imx8mp-evk.dtb: pcie@33800000: clock-names:1: 'pcie_bus' was expected > From schema: > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > imx8mp-evk.dtb: pcie@33800000: clock-names:2: 'pcie_phy' was expected > From schema: > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > > The bindings want 4 clocks for imx8mq (and imx8mp which seems similar): > * pcie > * pcie_bus > * pcie_phy > * pcie_aux > > Ignoring the order there is no pcie_phy clock anymore, it was removed in > commit 1840518ae7de ("clk: imx8mp: Remove the none exist pcie clocks"). I > was wondering why, because the PCIE_PHY_CLK_ROOT at register 0xa380 > inside CCM is listed in RM. > So there is a clock missing for 'pcie_phy' or the binding needs some update for > imx8mp, no? Hi Alexander: Thanks for your comments. I had confirmed with design team, the PCIE_PHY_CLK_ROOT at register 0xa380 is not used anymore on i.MX8MP PCIe. So I used to issue one patch to remove the useless code from clock driver. About the dt-binding of the i.MX8MP clocks, I would update the yaml later. BTW, i.MX8MP PCIe is similar to the i.MX8MM PCIe's. It's better to make reference to the i.MX8MM PCIe clocks definitions. Best Regards Richard Zhu > > Regards, > Alexander > > > + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, > > + <&clk IMX8MP_CLK_PCIE_AUX>; > > + assigned-clock-rates = <500000000>, <10000000>; > > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, > > + <&clk IMX8MP_SYS_PLL2_50M>; > > + vpcie-supply = <®_pcie0>; > > + status = "okay"; > > +}; > > + > > &snvs_pwrkey { > > status = "okay"; > > }; > > @@ -442,6 +484,19 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA > 0x400001c3 > > > > >; > > > > }; > > > > + pinctrl_pcie0: pcie0grp { > > + fsl,pins = < > > + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B > 0x61 /* open drain, pull up */ > > + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 > 0x41 > > + >; > > + }; > > + > > + pinctrl_pcie0_reg: pcie0reggrp { > > + fsl,pins = < > > + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 > 0x41 > > + >; > > + }; > > + > > pinctrl_pmic: pmicgrp { > > fsl,pins = < > > MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 > 0x000001c0 > > >