On Wed, Mar 23, 2022 at 5:15 PM dann frazier <dann.frazier@xxxxxxxxxxxxx> wrote: > > On Wed, Mar 23, 2022 at 09:49:04AM +0000, Marc Zyngier wrote: > > On Tue, 22 Mar 2022 17:27:36 +0000, > > Robin Murphy <robin.murphy@xxxxxxx> wrote: > > > > > > Originally, creating the dma_ranges resource list in pre-sorted fashion > > > was the simplest and most efficient way to enforce the order required by > > > iova_reserve_pci_windows(). However since then at least one PCI host > > > driver is now re-sorting the list for its own probe-time processing, > > > which doesn't seem entirely unreasonable, so that basic assumption no > > > longer holds. Make iommu-dma robust and get the sort order it needs by > > > explicitly sorting, which means we can also save the effort at creation > > > time and just build the list in whatever natural order the DT had. > > > > > > Signed-off-by: Robin Murphy <robin.murphy@xxxxxxx> > > > --- > > > > > > Looking at this area off the back of the XGene thread[1] made me realise > > > that we need to do it anyway, regardless of whether it might also happen > > > to restore the previous XGene behaviour or not. Presumably nobody's > > > tried to use pcie-cadence-host behind an IOMMU yet... > > > > This definitely restores PCIe functionality on my Mustang (XGene-1). > > Hopefully dann can comment on whether this addresses his own issue, as > > his firmware is significantly different. > > Robin, Marc, > > Adding just this patch on top of v5.17 (w/ vendor dtb) isn't enough to > fix m400 networking: I wouldn't expect it to given both the IB register selection changed and the 2nd dma-ranges entry is ignored. Can you (and others) try out this branch: git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git xgene-pci-fix It should maintain the same IB register usage for both cases and handle the error in 'dma-ranges'. Rob
