On Friday 25 February 2022 11:02:25 Bjorn Helgaas wrote: > On Fri, Feb 25, 2022 at 01:54:07PM +0100, Pali Rohár wrote: > > On Thursday 24 February 2022 15:28:11 Bjorn Helgaas wrote: > > > On Tue, Feb 22, 2022 at 05:31:57PM +0100, Pali Rohár wrote: > > > > This PCIe message is sent automatically by mvebu HW when link changes > > > > status from down to up. > > > > PCIe r6.0, sec 2.2.8.5 and 7.5.3.9, also say Set_Slot_Power_Limit must > > > be sent on a config write to Slot Capabilities. I don't really > > > understand that, since AFAICS, everything in that register is > > > read-only. But there must be some use case for forcing a message. > > > > I understood it in this way: Capabilities register is read-only hw-init > > and so firmware / driver can write initialization values into this > > register. And when firmware / driver is doing this write then Root port > > should send that Set_Slot_Power_Limit message. > > Sec 7.5.3.9 describes the behavior of Slot Capabilities in config > space, where it must be read-only. Firmware (or the mvebu driver) > must use a different mechanism to initialize the values. > > FWIW, I found this implementation note in PCIe r6.0, sec 6.9 that > explains why config writes to this read-only register would be useful: > > IMPLEMENTATION NOTE: AUTO SLOT POWER LIMIT DISABLE > > In some environments host software may wish to directly manage the > transmission of a Set_Slot_Power_Limit message by performing a > Configuration Write to the Slot Capabilities register rather than > have the transmission automatically occur when the Link transitions > from a non-DL_Up to a DL_Up status. This allows host software to > limit power supply surge current by staggering the transition of > Endpoints to a higher power state following a Link Down or when > multiple Endpoints are simultaneously hot-added due to cable or > adapter insertion. > > Bjorn Hm... I did not understand from this description what should happen when write operation is performed to the slot capabilities register. It is allowed to change content of this register? Or better question, what should write hook in pci-mvebu.c driver for slot capabilities do?
