On Wed, Feb 09, 2022 at 11:28:01AM -0500, Michael J. Ruhl wrote: > In order to do P2P communication the bridge ID of the platform > must be in the P2P device table. > > Update the P2P device table with a device id for the 3rd Gen > Intel Xeon Scalable Processors. > > Reviewed-by: Dan Williams <dan.j.williams@xxxxxxxxx> > Signed-off-by: Michael J. Ruhl <michael.j.ruhl@xxxxxxxxx> Updated the commit log to match previous similar patches and applied as below to pci/p2pdma for v5.18, thanks! Device ID 0x09a2 doesn't appear at https://pci-ids.ucw.cz/read/PC/8086 which means "lspci" won't be able to display a human-readable name for these devices. You can easily add a name at that same URL. Bjorn commit feaea1fe8b36 ("PCI/P2PDMA: Add Intel 3rd Gen Intel Xeon Scalable Processors to whitelist") Author: Michael J. Ruhl <michael.j.ruhl@xxxxxxxxx> Date: Wed Feb 9 11:28:01 2022 -0500 PCI/P2PDMA: Add Intel 3rd Gen Intel Xeon Scalable Processors to whitelist In order to do P2P communication the bridge ID of the platform must be in the P2P device table. Update the P2P device table with a device ID for the 3rd Gen Intel Xeon Scalable Processors. Link: https://lore.kernel.org/r/20220209162801.7647-1-michael.j.ruhl@xxxxxxxxx Signed-off-by: Michael J. Ruhl <michael.j.ruhl@xxxxxxxxx> Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> Reviewed-by: Dan Williams <dan.j.williams@xxxxxxxxx> > --- > drivers/pci/p2pdma.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c > index 1015274bd2fe..30b1df3c9d2f 100644 > --- a/drivers/pci/p2pdma.c > +++ b/drivers/pci/p2pdma.c > @@ -321,6 +321,7 @@ static const struct pci_p2pdma_whitelist_entry { > {PCI_VENDOR_ID_INTEL, 0x2032, 0}, > {PCI_VENDOR_ID_INTEL, 0x2033, 0}, > {PCI_VENDOR_ID_INTEL, 0x2020, 0}, > + {PCI_VENDOR_ID_INTEL, 0x09a2, 0}, > {} > }; > > -- > 2.31.1 >
