On Tue, Feb 22, 2022 at 04:50:23PM +0100, Pali Rohár wrote: > If x1/x4 mode is not set correctly then link with endpoint card is not > established. > > Use DTS property 'num-lanes' to deteriminate x1/x4 mode. I know this is already merged, but if tweaking for any other reason, s/deteriminate/determine/ > + * Set Maximum Link Width to X1 or X4 in Root Port's PCIe Link > + * Capability register. This register is defined by PCIe specification > + * as read-only but this mvebu controller has it as read-write and must > + * be set to number of SerDes PCIe lanes (1 or 4). If this register is > + * not set correctly then link with endpoint card is not established. True, everything in Link Capability is RO or HwInit, but that's for the architected access via config space. I think a device-specific mechanism like this is fair game as long as you do it before anybody can read it via config space. > + */ > + lnkcap = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); > + lnkcap &= ~PCI_EXP_LNKCAP_MLW; > + lnkcap |= (port->is_x4 ? 4 : 1) << 4; > + mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP);
