On Fri, Feb 11, 2022 at 03:32:58PM +0800, Richard Zhu wrote:
> In the i.MX6QP sabresd board(sch-28857) design, one external oscillator
> is used as the PCIe reference clock source by the endpoint device.
>
> If RC uses this oscillator as reference clock too, PLL6(ENET PLL) would
> has to be in bypass mode, and ENET clocks would be messed up.
>
> To keep things simple, let RC use the internal PLL as reference clock
> and always enable the external oscillator for endpoint device on
> i.MX6QP sabresd board.
>
> NOTE: This reference clock setup is used to pass the GEN2 TX compliance
> tests, and isn't recommended as a setup in the end-user design.
I do not quite follow. The commit log is all talking about external
oscillator reference clock, while code is playing 'vgen3' regulator.
Shawn
>
> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> ---
> arch/arm/boot/dts/imx6qp-sabresd.dts | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts
> index 480e73183f6b..083cf90bcab5 100644
> --- a/arch/arm/boot/dts/imx6qp-sabresd.dts
> +++ b/arch/arm/boot/dts/imx6qp-sabresd.dts
> @@ -50,8 +50,14 @@ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
> };
> };
>
> +&vgen3_reg {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> +};
> +
> &pcie {
> - status = "disabled";
> + status = "okay";
> };
>
> &sata {
> --
> 2.25.1
>
