On 2/1/2022 6:05 PM, Vidya Sagar wrote:
> Previously ASPM L1 Substates control registers (CTL1 and CTL2) weren't
> saved and restored during suspend/resume leading to L1 Substates
> configuration being lost post-resume.
>
> Save the L1 Substates control registers so that the configuration is
> retained post-resume.
>
Thanks Vidya for making this change.
I have applied your patch in v5.17-rc2 and did 100 cycles of
suspend/resume in a Alder lake based notebook which has
NVIDIA discrete GPU and it is working fine.
After Boot:
# lspci -d "0x10de:" -vvv|grep "L1SubCtl1"
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
After Suspend/resume without this patch:
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
After Suspend/resume with this patch:
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
Tested-by: Abhishek Sahu <abhsahu@xxxxxxxxxx>
Thanks,
Abhishek
> Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
> ---
> Hi,
> Similar patch was merged in the past through the commit 4257f7e008ea
> ("PCI/ASPM: Save/restore L1SS Capability for suspend/resume") but it later
> got reverted through the commit 40fb68c7725a as Kenneth R. Crudup
> <kenny@xxxxxxxxx> reported disk IO errors because of it. I couldn't spend much
> time debugging the issue back then, but taking a fresh look at the issue, it
> seems more like an issue with the platform in question than this change itself.
> Reason being that there are other devices that support ASPM L1 Sub-States
> on that platform (as observed in the lspci output mentioned at
> https://lore.kernel.org/linux-pci/53d3bd83-c0c2-d71f-9e5b-1dbdde55786@xxxxxxxxx/ )
> and assuming that L1 Sub-States are indeed enabled for those devices, there
> are no issues reported from those devices except from the NVMe drive.
> When it comes to the NVMe driver, the code at
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/nvme/host/pci.c?h=v5.17-rc2#n3008
> has some quirks for some of the models from Dell Inc and I'm wondering if
> the model on which the issue was observed might need a quirk of its own??
>
> So,
> Kenneth R. Crudup <kenny@xxxxxxxxx>
> Could you please try this patch on top of linux-next and collect more info?
> - 'sudo lspci -vvvv' output before and after hibernation
> - could you please confirm the working of this patch for non NVMe devices that
> support L1 Sub-States?
> - Could you please try "NVME_QUIRK_NO_DEEPEST_PS" and "NVME_QUIRK_SIMPLE_SUSPEND"
> quirks (one at a time) in check_vendor_combination_bug() API and see if it
> makes any difference?
>
> Thanks & Regards,
> Vidya Sagar
>
> drivers/pci/pci.c | 7 +++++++
> drivers/pci/pci.h | 4 ++++
> drivers/pci/pcie/aspm.c | 44 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 55 insertions(+)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 9ecce435fb3f..75a8b264ddac 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -1617,6 +1617,7 @@ int pci_save_state(struct pci_dev *dev)
> return i;
>
> pci_save_ltr_state(dev);
> + pci_save_aspm_l1ss_state(dev);
> pci_save_dpc_state(dev);
> pci_save_aer_state(dev);
> pci_save_ptm_state(dev);
> @@ -1723,6 +1724,7 @@ void pci_restore_state(struct pci_dev *dev)
> * LTR itself (in the PCIe capability).
> */
> pci_restore_ltr_state(dev);
> + pci_restore_aspm_l1ss_state(dev);
>
> pci_restore_pcie_state(dev);
> pci_restore_pasid_state(dev);
> @@ -3430,6 +3432,11 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev)
> if (error)
> pci_err(dev, "unable to allocate suspend buffer for LTR\n");
>
> + error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_L1SS,
> + 2 * sizeof(u32));
> + if (error)
> + pci_err(dev, "unable to allocate suspend buffer for ASPM-L1SS\n");
> +
> pci_allocate_vc_save_buffers(dev);
> }
>
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 3d60cabde1a1..5de1cfe07749 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -562,11 +562,15 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev);
> void pcie_aspm_exit_link_state(struct pci_dev *pdev);
> void pcie_aspm_pm_state_change(struct pci_dev *pdev);
> void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
> +void pci_save_aspm_l1ss_state(struct pci_dev *dev);
> +void pci_restore_aspm_l1ss_state(struct pci_dev *dev);
> #else
> static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
> static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
> static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
> static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
> +static inline void pci_save_aspm_l1ss_state(struct pci_dev *dev) { }
> +static inline void pci_restore_aspm_l1ss_state(struct pci_dev *dev) { }
> #endif
>
> #ifdef CONFIG_PCIE_ECRC
> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> index a96b7424c9bc..2c29fdd20059 100644
> --- a/drivers/pci/pcie/aspm.c
> +++ b/drivers/pci/pcie/aspm.c
> @@ -726,6 +726,50 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
> PCI_L1SS_CTL1_L1SS_MASK, val);
> }
>
> +void pci_save_aspm_l1ss_state(struct pci_dev *dev)
> +{
> + int aspm_l1ss;
> + struct pci_cap_saved_state *save_state;
> + u32 *cap;
> +
> + if (!pci_is_pcie(dev))
> + return;
> +
> + aspm_l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
> + if (!aspm_l1ss)
> + return;
> +
> + save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_L1SS);
> + if (!save_state)
> + return;
> +
> + cap = (u32 *)&save_state->cap.data[0];
> + pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL2, cap++);
> + pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, cap++);
> +}
> +
> +void pci_restore_aspm_l1ss_state(struct pci_dev *dev)
> +{
> + int aspm_l1ss;
> + struct pci_cap_saved_state *save_state;
> + u32 *cap;
> +
> + if (!pci_is_pcie(dev))
> + return;
> +
> + aspm_l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
> + if (!aspm_l1ss)
> + return;
> +
> + save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_L1SS);
> + if (!save_state)
> + return;
> +
> + cap = (u32 *)&save_state->cap.data[0];
> + pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL2, *cap++);
> + pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, *cap++);
> +}
> +
> static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
> {
> pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
