On Wed, 02 Feb 2022 19:56:14 -0800 Dan Williams <dan.j.williams@xxxxxxxxx> wrote: > From: Ben Widawsky <ben.widawsky@xxxxxxxxx> > > At this point the subsystem can enumerate all CXL ports (CXL.mem decode > resources in upstream switch ports and host bridges) in a system. The > last mile is connecting those ports to endpoints. > > The cxl_mem driver connects an endpoint device to the platform CXL.mem > protoctol decode-topology. At ->probe() time it walks its > device-topology-ancestry and adds a CXL Port object at every Upstream > Port hop until it gets to CXL root. The CXL root object is only present > after a platform firmware driver registers platform CXL resources. For > ACPI based platform this is managed by the ACPI0017 device and the > cxl_acpi driver. > > The ports are registered such that disabling a given port automatically > unregisters all descendant ports, and the chain can only be registered > after the root is established. > > Given ACPI device scanning may run asynchronously compared to PCI device > scanning the root driver is tasked with rescanning the bus after the > root successfully probes. > > Conversely if any ports in a chain between the root and an endpoint > becomes disconnected it subsequently triggers the endpoint to > unregister. Given lock dependencies the endpoint unregistration happens > in a workqueue asynchronously. If userspace cares about synchronizing > delayed work after port events the /sys/bus/cxl/flush attribute is > available for that purpose. > > Reported-by: Randy Dunlap <rdunlap@xxxxxxxxxxxxx> > Signed-off-by: Ben Widawsky <ben.widawsky@xxxxxxxxx> > [djbw: clarify changelog, rework hotplug support] > Signed-off-by: Dan Williams <dan.j.williams@xxxxxxxxx> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
