On Sun, 23 Jan 2022 16:31:46 -0800 Dan Williams <dan.j.williams@xxxxxxxxx> wrote: > From: Ben Widawsky <ben.widawsky@xxxxxxxxx> > > Recall that a CXL Port is any object that publishes a CXL HDM Decoder > Capability structure. That is Host Bridge and Switches that have been > enabled so far. Now, add decoder support to the 'endpoint' CXL Ports > registered by the cxl_mem driver. They mostly share the same enumeration > as Bridges and Switches, but witout a target list. The target of > endpoint decode is device-internal DPA space, not another downstream > port. > > Signed-off-by: Ben Widawsky <ben.widawsky@xxxxxxxxx> > [djbw: clarify changelog, hookup enumeration in the port driver] > Signed-off-by: Dan Williams <dan.j.williams@xxxxxxxxx> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
